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Nic30 / hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++
MIT License
194 stars 26 forks source link

Params are not working at hierarchical interfaces #3

Closed Nic30 closed 8 years ago

Nic30 commented 8 years ago 
ENTITY AxiLiteSlaveContainer IS
    GENERIC (
        ADDR_WIDTH : INTEGER := 8;
        DATA_WIDTH : INTEGER := 8
    );
    PORT (axi_ar_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
        axi_aw_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
        axi_r_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
...

the param from interface declaration is used instead

Nic30 commented 8 years ago

fixed