rm relicts of interface direction discoverry logic

Nic30 / hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

MIT License

194 stars 26 forks source link

Closed Nic30 closed 4 years ago

Nic30 commented 4 years ago

Nic30 commented 4 years ago

done a14a1f42d25a5ebe0a90ab25cad8eaf7bdc8aafc