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Nic30 / hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++
MIT License
194 stars 26 forks source link

Convert interfaces to HDL as well (VHDL records, SV interface) #32

Open Nic30 opened 4 years ago

Nic30 commented 4 years ago
  1. Extract interface as a VHDL records, SV interfaces and not just a separate signals.
  2. Nice methods for connecting rather than assignments.