Support for formal verification statements

Nic30 / hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

MIT License

194 stars 26 forks source link

Closed Nic30 closed 3 years ago

Nic30 commented 4 years ago

Add formal verification statement in same manner as constraint specification.

Nic30 commented 3 years ago

Nic30 commented 3 years ago

currently not enough time and the benefit would be severely limited due