IP core importing - Githubissues

Nic30 / hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

MIT License

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IP core importing #34

Open Nic30 opened 4 years ago

Nic30 commented 4 years ago

XCI contains parameters of ipcore. component.xml contains definitions of bus interfaces.

Import xci as a Unit instance.

component.xml with pregenerated values usually stored in .srcs/sources_1/bd/top_name/ip/ together with xci

lionheart117 commented 4 years ago

The xci is a format come from Xilinx, isn't it?

Nic30 commented 4 years ago

The one of formats used by Xilinx Vivado is IP-XACT (usually described using component.xml) from this it is possible to generate configured ip core (.xci file generated by vivado after ipcore is added to a project).

Nic30 commented 3 years ago

Example files generated in ipcore folder mem_axi_register_slice.zip