Nic30 / hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++
MIT License
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Complete tests for assignments to a cast or slice of registers #39

Closed Nic30 closed 3 years ago

Nic30 commented 3 years ago

Done after b64138fd22123b746374a3290f651c20808dd301

All assignments to a slices are split to elementary slices and final concatenation. All properties like default/nop value are kept asserting the functionality of syntax sugars like RtlSyncSignal. It also simplifies the analysis of the circuit as independent slice parts have own temporary signal or are directly driven from something.

https://github.com/Nic30/hwtLib/blob/master/hwtLib/tests/sertialization/assignToCastAndSlices.py#L199 https://github.com/Nic30/hwtLib/blob/master/hwtLib/tests/sertialization/AssignToASliceOfReg2a.vhd