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Nic30 / hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++
MIT License
194 stars 26 forks source link

If then else block can't find its block automaticaly #4

Closed Nic30 closed 8 years ago

Nic30 commented 8 years ago

rtlLvl/simpleRegister.py

IF ((rst = '1') AND (RISING_EDGE(clk))) THEN
     val <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, val'LENGTH));
END IF; 
IF ((( NOT(rst)) = '1') AND (RISING_EDGE(clk))) THEN
     val <= val_next;
END IF;

instead of :

IF ((rst = '1') AND (RISING_EDGE(clk))) THEN
     val <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, val'LENGTH));
ELSE
     val <= val_next;
END IF;
Nic30 commented 8 years ago

fixed