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Nic30 / hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++
MIT License
200 stars 27 forks source link

Condition tree rework #8

Closed Nic30 closed 6 years ago

Nic30 commented 6 years ago

Currently If-then-else and other condition containers are constructed in HDL rendering phase. This means every Assignment instance has list of it's conditions and condition containers are resolved from them. This makes thing complicated and slow.

This has to be removed and replaced with condition tree with hierarchy represented by real objects. Every object has to have reference on it's parent and has to have specified where it is in the parent.

Every RtlSignal then will have only top condition container in it's drivers or endpoints.

Nic30 commented 6 years ago

done in 092d045308e73fac34050d7625c0a946744b0d88