The Verilator updates the memories based on verilog code. However it is very practical to be able to intialize memory/register from python python as it is very useful tool during debugging and it is best way how to avoid too much compilations of the same circuit just with different configuration.
Now the memories inside of hierarchy can not be updated as it is banned in order to prevent accessing of read only things in simulation. However during initialisation phase it should be allowed.
Problem is hat the Verilator overwrites the memories during it's own intialisation which takes place after the initialization from python.
The Verilator updates the memories based on verilog code. However it is very practical to be able to intialize memory/register from python python as it is very useful tool during debugging and it is best way how to avoid too much compilations of the same circuit just with different configuration.
Now the memories inside of hierarchy can not be updated as it is banned in order to prevent accessing of read only things in simulation. However during initialisation phase it should be allowed.