Nitcloud / Digital-IDE

在vscode上的数字设计开发插件
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"show netlist" option cannot show correctly when other module instantiation in top module #57

Open Collect-diamond opened 1 year ago

Collect-diamond commented 1 year ago

I defined 2 verilog modules, one for DFF and one for EXAMP, I instantiated the DFF module twice in the EXAMP module, but when I use the "show netlist" option to view the schematic, it shows the schematic of the DFF module, while when I change the name of the EXAMP module to A (the initials of the module are sorted before D), the schematic is correct. is it a bug?

Nitcloud commented 1 year ago

The issue has been logged, can you please provide sample code for testing?

Collect-diamond commented 1 year ago

D_FF.v

module D_FF(clk,d,q);
    output reg q;
    input clk,d;
    always @ (posedge clk)
        q<=d;
endmodule

TEST.v (module A or E)

module E (clk,d,a,q);
    output  q;
    input clk,d,a;

    wire d1;
    wire q1;

    D_FF dff1(.clk(clk),.d(d1),.q(q1));
    D_FF dff2(.clk(q1),.d(d),.q(q));

    or (d1,a,q);

endmodule