NoSuchProcess / arm-cpu-core

Automatically exported from code.google.com/p/arm-cpu-core
0 stars 0 forks source link

STM stores old value of register loaded from memory by previous operation #3

Open GoogleCodeExporter opened 8 years ago

GoogleCodeExporter commented 8 years ago
What steps will reproduce the problem?
1. write small program which contains next instructions in specified order:
    MOV r0,#0xa50000
    LDR r0,=0x123456
    STM r1,{r0,r2}
2. compile
3. run

What is the expected output? What do you see instead?
Expected output is writing value 0x123456 and then value of R2 to memory 
starting from R1. But actual result is write of 0xa50000 and then value of R2.

Original issue reported on code.google.com by Sergey.B...@gmail.com on 6 Oct 2014 at 9:37

GoogleCodeExporter commented 8 years ago
To fix it just add code_is_stm (code_is_ldm & !code[20]) to wait_en:

-assign wait_en = (code_rm_vld & cha_vld & (cha_num == code_rm_num)) | 
(code_rm_vld & to_vld & (to_num == code_rm_num)) | (code_rm_vld &
 go_vld & (go_num == code_rm_num)) | (code_rs_vld & cha_vld & (cha_num == code_rs_num)) | (code_rs_vld & to_vld & (to_num == code_rs_num
)) | (code_rs_vld & go_vld & (go_num == code_rs_num)) | (code_rn_vld & cha_vld 
& (code_rn_num == cha_num)) |  (code_rnhi_vld & cha_vld &
 (code_rnhi_num == cha_num)) | (code_rm_vld & (ldm_vld & ~hold_en) & (ldm_num == code_rm_num)) | (code_rs_vld & (ldm_vld & ~hold_en) & (
ldm_num == code_rs_num));
+assign wait_en = (code_rm_vld & cha_vld & (cha_num == code_rm_num)) | 
(code_rm_vld & to_vld & (to_num == code_rm_num)) | (code_rm_vld &
 go_vld & (go_num == code_rm_num)) | (code_rs_vld & cha_vld & (cha_num == code_rs_num)) | (code_rs_vld & to_vld & (to_num == code_rs_num
)) | (code_rs_vld & go_vld & (go_num == code_rs_num)) | (code_rn_vld & cha_vld 
& (code_rn_num == cha_num)) |  (code_rnhi_vld & cha_vld &
 (code_rnhi_num == cha_num)) | (code_rm_vld & (ldm_vld & ~hold_en) & (ldm_num == code_rm_num)) | (code_rs_vld & (ldm_vld & ~hold_en) & (
ldm_num == code_rs_num)) | (cha_vld & code_is_ldm & !code[20]);

As result, if cpu stores one or more registers changed by previous operation it 
halts for 1 clock.

Original comment by Sergey.B...@gmail.com on 9 Oct 2014 at 10:59