Ported open loop control from dev kit to actual platform
Hooked up ADC interrupt to queue data to controller
Created PWM actor task that actually writes the PWM data
Initialized controller for both motors
Created and verified shared memory between the processors
Hooked up DMA stream to both pieces of shared memory
Created IPCC interface to abstract comms between cores
Hooked up hardware semaphores for alerting other core
Added in microsecond timer
Fixed FOC control pointer stuff
Notes
I am so sorry for the size of this commit I got carried away and just did stuff.
Note that IPCC comms are NOT fully verified yet. There are a lot of different ways of doing this and I want to really get a good idea of what responsibilities we should designate to each core. I think I am heavily leaning towards having the core be used solely for diagnostics and runtime behavior analysis. (i.e. CAN bus interface, serial interface, plotting task performance, monitoring temperatures, etc). That way we can kinda have them both running separate and not super dependent on eachother but still have them be extremely advantageous to use.
Test Cases
Tested write and read to and from each piece of shared memory
To Do
Any remaining things that need to get done
[ ] Hardware semaphore only triggers interrupt once
Changes
This commit is ginormous I am so sorry
Notes
I am so sorry for the size of this commit I got carried away and just did stuff.
Note that IPCC comms are NOT fully verified yet. There are a lot of different ways of doing this and I want to really get a good idea of what responsibilities we should designate to each core. I think I am heavily leaning towards having the core be used solely for diagnostics and runtime behavior analysis. (i.e. CAN bus interface, serial interface, plotting task performance, monitoring temperatures, etc). That way we can kinda have them both running separate and not super dependent on eachother but still have them be extremely advantageous to use.
Test Cases
To Do
Any remaining things that need to get done