Quartus 13.1 build failure: Verilog HDL error at nios_system.v(225): '1 is a SystemVerilog feature

[rtucker]

With Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition, ./build-bladerf.sh -r hosted -s 115 bombs out with:

Error (10839): Verilog HDL error at nios_system.v(225): '1 is a SystemVerilog feature File: /home/rtucker/tmp/bladerf-20131207/bladeRF/hdl/quartus/work/db/ip/nios_system/nios_system.v Line: 225
Error (10170): Verilog HDL syntax error at nios_system.v(225) near text ' File: /home/rtucker/tmp/bladerf-20131207/bladeRF/hdl/quartus/work/db/ip/nios_system/nios_system.v Line: 225
Error (10170): Verilog HDL syntax error at nios_system.v(225) near text "'";  expecting ")" File: /home/rtucker/tmp/bladerf-20131207/bladeRF/hdl/quartus/work/db/ip/nios_system/nios_system.v Line: 225
Error (10112): Ignored design unit "nios_system" at nios_system.v(6) due to previous errors File: /home/rtucker/tmp/bladerf-20131207/bladeRF/hdl/quartus/work/db/ip/nios_system/nios_system.v Line: 6
Info (12021): Found 0 design units, including 0 entities, in source file db/ip/nios_system/nios_system.v

Weird.

[tobbad]

On Quartus 13.1 the generation of the nios_system.v file from a variable type of STD_LOGIC will result in a verilog line of: i2c_master_top #( .ARST_LVL ('1') ) oc_i2c_master_0 ( which will stop the build of the bitstream. Changing the interface property of the ARST_LVL parameter to integer would solve thie issue. Change: add_parameter ARST_LVL STD_LOGIC 0 "" ... set_parameter_property ARST_LVL TYPE STD_LOGIC To add_parameter ARST_LVL STD_LOGIC 0 "" ... set_parameter_property ARST_LVL TYPE INTEGER

[polygon]

I ran into the same problem. I can confirm that tobbad's change fixes the issue. Thanks!

[bpadalino]

Fixed in 61130fb4abd0885ea395d44678b928dddca0abc3 with a sed script in build_bladerf.sh