Closed jmichelp closed 10 years ago
bpadalino
commented
10 years ago Yeah, that sounds like a good idea. Do you care to have an adjustable bandwidth to the IIR filter that gets put in there to try to track the DC component? Do you think it would be useful to be able to read the settled I and Q signals?
gitfoxi
commented
10 years ago I've just finally got my bladerf up and running and I'm really excited to see it work. I don't really know where the project is at. But, in-general, things like FIR, IIR, decimation, FFT, IQ phase/gain balancing, ADC offset correction (including DC), automatic gain control, digital symbol alignment, forward error correction are all things you might try and offload.
In addition to the FPGA, DSP can be implemented in the FX3. This surprised me, but it's in their documentation that you can offload stream processing to it.
Lots of fun to be done. With only 5 people committing to the repo so far, I don't know how far we'll get. Hopefully now that it's easier to build a working system there will be more.
bpadalino
commented
10 years ago The IQ correction blocks are already in the latest FPGA images. You have to set them manually, though.
I agree, though, that lots of interesting things can be pushed off to the FPGA to make the host code less processing intensive.
The programmable single pole IIR filter is probably where this will end up going along with a 'hold' signal so that the DC stops jumping around.
AGC would be great to put into the NIOS, but would also be nice to have a 'hold'.
gitfoxi
commented
10 years ago I'm trying to figure out what's this NIOS? It looks like it's a soft CPU core taking up about 2k LEs and having maybe 80 MIPS performance.
It seems like it's being included in the project but I can't really tell why. There doesn't seem to be any program source for it. Maybe I can't find where it's programmed in the tree or maybe it's just not doing much yet?
...
To answer my own question, I find the program here:
hdl/fpga/ip/altera/nios_system/software/lms_spi_controller/lms_spi_controller.c
So NIOS is running a program already talking to the RFIC which is why it's a good place for AGC. Makes sense now.
jmichelp
commented
10 years ago It depends on how fast this can be added to the VHDL project. But it's time greedy, configurable filters can come later. I don't think the URSP have any.configuration on that kind of filter. I have a coworker that definitely knows FPGAs and that may have enough time to compute the correct filter on matlab and add it to the VHDL project if you want (and of course I can test his work before issuing the pull request)
jynik
commented
10 years ago Closing this issue for the time being, as LMS calibrations and DC offset calibration tables are being introduced into libbladeRF, with the objective of minimizing DC offset to maximize dynamic range (without burning CPU cycles).
While there is some residual DC offset, when well-calibrated, it's usually a few LSBs (or fractions of).
As always, patches are welcome - if there's interest in further HDL developments here, feel free to open a pull request or new issue to further discuss.
This is an improvement request to add a DC remover block in the FPGA (just like it is done in Ettus USRP2) to avoid wasting CPU computation on that and thus resulting in a much cleaner signal.