LMS Failures persist after FPGA v0.1.1

[jynik]

While FPGA v0.1.1 introduces timing constraints that addressed, LMS accesses still appear to fail.

It was reported that tuning to 1.575e6 and running a cal lms fails with RXVGA2 values coming back as 31's. This procedure yields a "Bad DC_REGVAL" on one of my devices (but not at other frequencies.)

[jynik]

While I forsee the 31's possibly being timing-related, I'm unsure about the bad LPF DC_REGVAL reports, considering that it works fine at one frequency, but then fails consistently for another. Furthermore, slowing down the clock rate to relax timing a bit doesn't seem to have an affect. Will provide more info here as we investigate further.

As a sanity check, I've built some v0.1.1 FPGA images with slower LMS SPI clock rates, and figured I might as well share them here. If folks are seeing RXVGA2 values of 31's, I suspect trying a 20MHz image or lower may cause this to subside (i.e., mask the underlying timing issue that we need to get fixed).

https://www.nuand.com/~jon/issues/341/hostedx115_20MHz_SPI0.rbf https://www.nuand.com/~jon/issues/341/hostedx115_5MHz_SPI0.rbf https://www.nuand.com/~jon/issues/341/hostedx115_1MHz_SPI0.rbf https://www.nuand.com/~jon/issues/341/hostedx115_200KHz_SPI0.rbf

https://www.nuand.com/~jon/issues/341/hostedx40_20MHz_SPI0.rbf https://www.nuand.com/~jon/issues/341/hostedx40_5MHz_SPI0.rbf https://www.nuand.com/~jon/issues/341/hostedx40_1MHz_SPI0.rbf https://www.nuand.com/~jon/issues/341/hostedx40_200KHz_SPI0.rbf

[jynik]

I've added some retry logic to the LMS DC calibration. It appeared that having gains too high were causing the "Bad DC_REGVAL" failures. With each retry, the gains are backed down.

This change was merged into master in 1c01c04c39c470641ffad6570dc90a0ed7e3993a. I have not seen this failure since, using multiple boards, at various frequencies.

[jynik]

Between the change in 1c01c04 and no more reports of 31's (including the boards I've tested), I'm marking this issue closed.