Closed bglod closed 5 years ago
Pull request for Part 1 of this endeavor. https://github.com/Nuand/bladeRF/pull/634
Part 2 has an issue that may cause bad things to happen on xA9 boards. I will revisit this at a later date.
In the mean time, if you really need this feature, modify this line: https://github.com/Nuand/bladeRF/blob/6737d7b02be1dcb38c1e02ca31e88fe3d99b783a/host/libraries/libbladeRF/include/bladeRF1.h#L76 To read:
#define BLADERF_FLASH_TOTAL_SIZE (128 << 17)
And rebuild bladeRF.
This will make the host think the SPI flash is 128 Mbit and allow an xA9 image to be written to flash. Note that this modification will also work with x40, x115, and xA4 devices, but size checking will not detect flash overflows because these devices only have 32 Mbit flashes. This is unlikely to cause problems for most use cases because the host software verifies the FPGA file sizes, but it is something to be aware of.
This is now fixed and merged into master, and will be in the next release coming soooooooon!
Closing.
Need to fix loading of xA9 FPGAs via SPI flash.