Closed rtucker closed 6 years ago
possibly #395 coming back to roost
As a workaround, the v0.8.0 FPGA image for the x115 seems to work okay: https://www.nuand.com/fpga_images/
My current theory is that the SPI controller/arbiter are in the wrong clock domain, resulting in unexpected (and incorrectly-defined) clock domain crossings. Some builds will be fine, others will fail.
Forum thread: https://nuand.com/forums/viewtopic.php?f=4&t=4964
Performing
cal table agc rx
with 2018.08 and FPGA 0.7.3 (official release) on an x115 fails:(note: omitted most si5338 and lms setup read/writes)