Timing violations in oneAPI board_test sample from eval script

[sidsahay]

Step 53 of the eval script (compile sample oneAPI application board_test) fails with a timing violation:

[ 50%] Building CXX object src/CMakeFiles/board_test.fpga.dir/board_test.cpp.o
[100%] Linking CXX executable ../board_test.fpga
warning: -reuse-exe file '/ofs/ofs-2023.1-1/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/build/board_test.fpga' not found; ignored
aoc: Adding Quartus fast-compile settings.
Warning: Circuit performance will be significantly degraded.
aoc: Compiling for FPGA. This process may take several hours to complete.  Prior to performing this compile, be sure to check the reports to ensure the design will meet your performance targets.  If the reports indicate performance targets are not being met, code edits may be required.  Please refer to the oneAPI FPGA Optimization Guide for information on performance tuning applications for FPGAs.
aoc: Warning: A timing failure has been detected in the outputted binary. There were 18 timing violations,
with the worst one being a Setup failure of 4153ps on clock:
 sys_pll|iopll_0_clk_sys                                  
Consider doing one or more of the following:
  - Recompiling with a different seed (using -Xsseed=<S>).
  - Reducing the area usage of your design.
  - If you are using a custom BSP, discuss the failure with your BSP vendor.
llvm-foreach: 
icpx: error: fpga compiler command failed with exit code 42 (use -v to see invocation)
icpx: note: diagnostic msg: The FPGA image generated during this compile contains timing violations and may produce functional errors if used. Refer to the Intel oneAPI DPC++ FPGA Optimization Guide section on Timing Failures for more information.
make[3]: *** [src/CMakeFiles/board_test.fpga.dir/build.make:97: board_test.fpga] Error 42
make[3]: *** Deleting file 'board_test.fpga'
make[2]: *** [CMakeFiles/Makefile2:208: src/CMakeFiles/board_test.fpga.dir/all] Error 2
make[1]: *** [CMakeFiles/Makefile2:241: src/CMakeFiles/fpga.dir/rule] Error 2
make: *** [Makefile:189: fpga] Error 2
Generating Log File with date and timestamp
Log file written to /ofs/ofs-2023.1-1/log_files/n6001_log_2023_07_26-201846/ofs_n6001_eval.log

Wed Jul 26 08:54:40 PM EDT 2023

Hardware: Silicom N6010 (N6001 platform), Intel Core i9-13900k, 64GB RAM. Software: Quartus 23.1, oneAPI 2023.1, OFS 2023.1, Ubuntu 22.04 with 6.2-dfl kernel.

Steps to Reproduce: Followed eval script steps to configure PF/VF, build the FIM, the PR tree, and compiled and executed hello_world BBB example (step 37-38) without any issues. For oneAPI, followed everything from step 39 (check oneAPI versions) until step 53 (compile sample board_test application) where this issue occurs.

I am able to successfully build and run some other oneAPI programs (like the cholesky example) on the FPGA card. It also appears the oneAPI compilation is using a "flat" flow (afu_flat) instead of only compiling the kernels? (because the n6001 BSP only has afu_flat as a compile/revision option in board_spec.xml) Is this expected?

[akasharo]

Hi Siddarth,

can you try adding the command -Xsseed=value to the evalution script option 45, so it will look something like this

cmake -DUSER_HARDWARE_FLAGS=-Xsseed=1 -DFPGA_DEVICE=$IOFS_BUILD_ROOT/oneapi-asp/$ADP_PLATFORM:$ONEAPI_BOARD_NAME ..

so in the above the seed value is changed to 1 but you can experiment with different seed values until you get a timing closed design.

also when you cloned the oneAPI-samples which tag did you use?

lastly you mentioend this is your set up

Software: Quartus 23.1, oneAPI 2023.1, OFS 2023.1, Ubuntu 22.04 with 6.2-dfl kernel.

but this doesnt match the Best Known Configuration in ths table below

https://ofs.github.io/hw/common/user_guides/oneapi_asp/ug_oneapi_asp/#23-prerequisites

Please let me know your feedback?

thanks

Akash

[cohensus]

Hi Siddarth, We will close this issue. Please re-open if you are still facing an issue.