The original SDC assignments for the EMIF clocks were wrong and led to timing violations in the analyses because the clock domains weren't set to be asynchronous.
Collateral (docs, reports, design examples, case IDs):
Tests added:
none
Tests run:
ran board_test compile for n6001, iseries-dk and fseries-dk ASPs
Description
The original SDC assignments for the EMIF clocks were wrong and led to timing violations in the analyses because the clock domains weren't set to be asynchronous.
Collateral (docs, reports, design examples, case IDs):
Tests added:
none
Tests run:
ran board_test compile for n6001, iseries-dk and fseries-dk ASPs