Does optee_os use both TTBR0_EL1 and TTBR1_EL1 in AArch64?

[yw-kim]

I am an engineer studying optee_os. My name is yaewon.

I have a question about using mmu in the aarch64 architecture in optee_os.

In your optee documentation, optee_os is using both ttbr0_el1 and ttbr1_el1. (https://optee.readthedocs.io/architecture/core.html#mmu)

However, looking at the actual optee_os code, it appears to use only ttbr0_el1.

You can see that the core_mmu_set_user_map () function only sets ttbr0_el1 for the user map.

In the core_init_mmu_regs () function, TCR_EL1.EPD1 is set to TCR_EPD1 (1), which disables the use of TTBR1_EL1.

I look forward to your answer.

void core_init_mmu_regs(void)
{
 . . . . . .
/* Disable the use of TTBR1 */
    tcr |= TCR_EPD1;

    /*
     * TCR.A1 = 0 => ASID is stored in TTBR0
     * TCR.AS = 0 => Same ASID size as in Aarch32/ARMv7
     */

    write_tcr_el1(tcr);
    write_ttbr0_el1(ttbr0);
    write_ttbr1_el1(0);
}

void core_mmu_set_user_map(struct core_mmu_user_map *map)
{
. . . . 
. . . .
/* Set the new map */
    if (map && map->user_map) {
        l1_xlation_table[0][get_core_pos()][user_va_idx] =
            map->user_map;
#ifdef CFG_CORE_UNMAP_CORE_AT_EL0
        l1_xlation_table[1][get_core_pos()][user_va_idx] =
            map->user_map;
#endif
        dsb();  /* Make sure the write above is visible */
        ttbr |= ((uint64_t)map->asid << TTBR_ASID_SHIFT);
        write_ttbr0_el1(ttbr);
        isb();
    } else {
        l1_xlation_table[0][get_core_pos()][user_va_idx] = 0;
#ifdef CFG_CORE_UNMAP_CORE_AT_EL0
        l1_xlation_table[1][get_core_pos()][user_va_idx] = 0;
#endif
        dsb();  /* Make sure the write above is visible */
    }
}

[jenswi-linaro]

You're correct in your observation. For AArch64 OP-TEE is not using TTBR1. However, it is used in AArch32 with short descriptor tables (CFG_WITH_LPAE=n).

[yw-kim]

Thank you for the clear answer.