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OSCPU / NutShell

RISC-V SoC designed by students in UCAS
https://oscpu.github.io/NutShell-doc/
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能否提供Golden的TopMain.v文件? Vivado BD创建失败, 因为NutShell模块的port不被识别为io_mem AXI口 #51

Closed huangping6686 closed 3 years ago

huangping6686 commented 3 years ago

您好! 能否提供正确的TopMain.v文件,供参考? 我使用0.6.3的mill创建了TopMain.v文件, 在fpga目录下, 使用pynq板卡, 创建vivado工程时,得到错误: ########## Vivado ERROR LOG ######## WARNING: [BD 5-232] No interface pins matched 'get_bd_intf_pins NutShell_0/io_mem' ERROR: [BD 5-106] Arguments to the connect_bd_intf_net command cannot be empty. ERROR: [Common 17-39] 'connect_bd_intf_net' failed due to earlier errors.

while executing

"connect_bd_intf_net -intf_net NutShell_0_io_mem [get_bd_intf_pins io_mem] [get_bd_intf_pins NutShell_0/io_mem]" (procedure "create_hier_cell_rv_system" line 84) invoked from within "create_hier_cell_rv_system [current_bd_instance .] rv_system" (procedure "create_root_design" line 61) invoked from within "create_root_design """ (file "board/pynq/bd/standalone.tcl" line 1359)

while executing

"source ${tcl_file}" (procedure "add_bd" line 2) invoked from within "add_bd ${bd_dir}/standalone.tcl" invoked from within "if {${standalone} == "true"} { add_bd ${bd_dir}/standalone.tcl make_wrapper -files [get_files *system_top.bd] -top add_files -norecurse -fileset..." (file "board/pynq/../common.tcl" line 55)

while executing

"source ${script_dir}/../common.tcl" (file "board/pynq/mk.tcl" line 17)

原因是iomem* 接口不被识别为 BD的AXI interface;
image 可以通过修改TopMain.v, 添加vivado AXI interface的描述, workaround这个问题, 但是 io_mmio_req_bits_cmd信号不是AXI标准信号, 该如何修改? image

还请指导一下!

感谢 Ping

谢谢! Ping

AugustusWillisWang commented 3 years ago

您好! 这一现象出现的原因是没有生成面向 FPGA 的 verilog 代码, 而是面向仿真环境的 verilog.

请检查生成 verilog 时使用的参数. 以仅生成面向 pynq FPGA 的 verilog 为例, 应使用的命令是:

make verilog BOARD=pynq

您可以参考项目根目录下的 Readme 来使用正确的命令生成 verilog / vivado project.

NutShell的顶层接口定义在NutShell.scala, 您可以参考这一文件来获取更多细节.

huangping6686 commented 3 years ago

感谢您的迅速答复; 用 make verilog BOARD=pynq, 已经解决了问题; 祝好!