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Problems when generating verilog #3

Closed Emin017 closed 1 year ago

Emin017 commented 1 year ago

在Ubuntu 22.04(amd64)环境下使用该工程，当chisel代码中加入Blackbox的addPath后，生成的verilog中会多出一行未注释的说明代码，导致无法通过verilator仿真

// ----- 8< ----- FILE "firrtl_black_box_resource_files.f" ----- 8< -----

build/build/dpi.v

将useMFC变量改成false后会将verilog文件复制到build文件夹下（符合Chisel文档对Blackbox中该功能的描述） 请问这是使用MFC后预期的正常生成结果吗？

另外在M2 Macbook上使用该工程在IDEA中生成verilog的时候(useMFC=true)会出现如下报错

Running CIRCT: 'firtool -format=fir -warn-on-unprocessed-annotations -verify-each=false -disable-infer-rw -dedup -annotation-file Core.anno.json < $input'
------------------------------------------------------------------------------
Error: firtool failed.
ExitCode:
-1
STDOUT:

STDERR:

------------------------------------------------------------------------------
Exception in thread "main" firrtl.options.StageError: 
    at circt.stage.phases.CIRCT.transform(CIRCT.scala:179)
    at circt.stage.phases.CIRCT.transform(CIRCT.scala:45)
    at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280)
    at firrtl.Utils$.time(Utils.scala:181)
    at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280)
    at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:169)
    at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:165)
    at scala.collection.immutable.List.foldLeft(List.scala:79)
    at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
    at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
    at firrtl.options.PhaseManager.transform(DependencyManager.scala:443)
    at circt.stage.CIRCTStage.run(CIRCTStage.scala:44)
    at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
    at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
    at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
    at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
    at firrtl.options.Translator.transform(Phase.scala:248)
    at firrtl.options.Translator.transform$(Phase.scala:248)
    at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
    at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47)
    at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:169)
    at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:165)
    at scala.collection.immutable.List.foldLeft(List.scala:79)
    at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47)
    at logger.Logger$.$anonfun$makeScope$2(Logger.scala:137)
    at scala.util.DynamicVariable.withValue(DynamicVariable.scala:59)
    at logger.Logger$.makeScope(Logger.scala:135)
    at firrtl.options.Stage.transform(Stage.scala:47)
    at firrtl.options.Stage.transform(Stage.scala:17)
    at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280)
    at firrtl.Utils$.time(Utils.scala:181)
    at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280)
    at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:169)
    at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:165)
    at scala.collection.immutable.List.foldLeft(List.scala:79)
    at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
    at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
    at firrtl.options.PhaseManager.transform(DependencyManager.scala:443)
    at circt.stage.ChiselStage.run(ChiselStage.scala:44)
    at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
    at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
    at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
    at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
    at firrtl.options.Translator.transform(Phase.scala:248)
    at firrtl.options.Translator.transform$(Phase.scala:248)
    at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
    at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47)
    at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:169)
    at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:165)
    at scala.collection.immutable.List.foldLeft(List.scala:79)
    at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47)
    at logger.Logger$.$anonfun$makeScope$2(Logger.scala:137)
    at scala.util.DynamicVariable.withValue(DynamicVariable.scala:59)
    at logger.Logger$.makeScope(Logger.scala:135)
    at firrtl.options.Stage.transform(Stage.scala:47)
    at firrtl.options.Stage.execute(Stage.scala:58)
    at Core.Elaborate$.delayedEndpoint$Core$Elaborate$1(Elaborate.scala:10)
    at Core.Elaborate$delayedInit$body.apply(Elaborate.scala:5)
    at scala.Function0.apply$mcV$sp(Function0.scala:39)
    at scala.Function0.apply$mcV$sp$(Function0.scala:39)
    at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:17)
    at scala.App.$anonfun$main$1(App.scala:76)
    at scala.App.$anonfun$main$1$adapted(App.scala:76)
    at scala.collection.IterableOnceOps.foreach(IterableOnce.scala:563)
    at scala.collection.IterableOnceOps.foreach$(IterableOnce.scala:561)
    at scala.collection.AbstractIterable.foreach(Iterable.scala:926)
    at scala.App.main(App.scala:76)
    at scala.App.main$(App.scala:74)
    at Core.Elaborate$.main(Elaborate.scala:5)
    at Core.Elaborate.main(Elaborate.scala)

经测试，执行make verilog也会出现类似错误 而将useMFC变量的值改为false后能正常生成verilog

rewired-gh commented 1 year ago

因为在 M2 Macbook 上使用的是 macOS 系统，而这个项目提供的 firtool 是为 Linux 构建的（ELF 格式）。由于 CIRCT 项目（firtool 所在的项目）并没有提供适用于 Apple Silicon 的二进制构建，于是我自己构建了一个能够在 Apple Silicon 和 Intel 平台上运行的 firtool 二进制可执行文件。如果你需要的话可以用 https://github.com/rewired-gh/open-mips-exercise/tree/main/utils 这个目录下的文件替换掉原本 utils 项目下的文件，然后应该就能在 M2 Macbook 正常使用 CIRCT 进行 elaborate。

Emin017 commented 1 year ago

因为在 M2 Macbook 上使用的是 macOS 系统，而这个项目提供的 firtool 是为 Linux 构建的（ELF 格式）。由于 CIRCT 项目（firtool 所在的项目）并没有提供适用于 Apple Silicon 的二进制构建，于是我自己构建了一个能够在 Apple Silicon 和 Intel 平台上运行的 firtool 二进制可执行文件。如果你需要的话可以用 https://github.com/rewired-gh/open-mips-exercise/tree/main/utils 这个目录下的文件替换掉原本 utils 项目下的文件，然后应该就能在 M2 Macbook 正常使用 CIRCT 进行 elaborate。

好的，非常感谢

sequencer commented 1 year ago

FYI, firtool is available in Nix since https://github.com/NixOS/nixpkgs/pull/214870 merged

Emin017 commented 1 year ago

But there is still a problem，content of the file "firrtl_black_box_resource_files.f" will be merged into the verilog file,which will cause the verilator simulation error. I am using my self-made shell script to remove these contents, is there a better solution？

sequencer commented 1 year ago

Split modules

Emin017 commented 1 year ago

Thanks everyone, my problem has been solved