Some wrong about verilog generate

[JimpleM]

When I use generate ... endgenerate in verilog, the yosys-sta could not generate the timing report because of the following error.

WARNING: Logging before InitGoogleLogging() is written to STDERR
I20240712 11:17:35.381661 14494 Sta.cc:320] read verilog file /Documents/ysyx/yosys-sta/result/test-500MHz/test.netlist.fixed.v start
E20240712 11:17:35.384013 14494 mVerilogParse.y:617] Error found in line 4607 in verilog file /Documents/ysyx/yosys-sta/result/test-500MHz/test.netlist.fixed.v
F20240712 11:17:35.384020 14494 VerilogReader.cc:620] Read verilog file failed.
*** Check failure stack trace: ***

So I read the ***.netlist.fixed.v and find that the code suddenly stop as followed.

wire \gpr[8][17] ;
wire \gpr[8][18] ;
wire \gpr[8][19] ;
wire \gpr[8][1] ;
wire \gpr[8][20] ;
wire

But I read the ***.netlist.syn.v, the generated code is exactly what I expected.

  \$paramod$7f9e490b9ced5d8980eed022c7283e4d4d2c8983\DFF  \genblk1[9].genblk1.regfile_dff  (
    .clock(clock),
    .din(reg_rd_data),
    .dout({ \gpr[9][31] , \gpr[9][30] , \gpr[9][29] , \gpr[9][28] , \gpr[9][27] , \gpr[9][26] , \gpr[9][25] , \gpr[9][24] , \gpr[9][23] , \gpr[9][22] , \gpr[9][21] , \gpr[9][20] , \gpr[9][19] , \gpr[9][18] , \gpr[9][17] , \gpr[9][16] , \gpr[9][15] , \gpr[9][14] , \gpr[9][13] , \gpr[9][12] , \gpr[9][11] , \gpr[9][10] , \gpr[9][9] , \gpr[9][8] , \gpr[9][7] , \gpr[9][6] , \gpr[9][5] , \gpr[9][4] , \gpr[9][3] , \gpr[9][2] , \gpr[9][1] , \gpr[9][0]  }),
    .reset(reset),
    .wen(\gpr_wen[9] )
  );

code: test.zip

[sashimi-yzh]

We have updated iEDA. Please try the following.

cd yosys-sta
git pull origin master
rm -rf bin
make init
# try to generate the timing report of your design