core as a slave

[garengllc]

Not an issue, more of a question. I stumbled upon your core (thanks for putting it out into the community) while doing some research. I have a design with an STM32H microcontroller interfaced to a Kintex-7, and plan to have the STM as the HyperBUS master. Cypress supplies a Xilinx HyperBUS controller, but only in master mode. Before I started looking at a level of effort to attempt to come up with a controller of my own, I started poking around to see if someone else had done it yet. Your design seemed close, but I do not believe it can act as a slave, correct? Over the course of implementing this, did you ever run across a core that could act in slave mode?

TIA

[OVGN]

Hello, @garengllc

Your design seemed close, but I do not believe it can act as a slave, correct?

Yes, it is not designed to be a slave, it is a master.

Over the course of implementing this, did you ever run across a core that could act in slave mode?

Actually no. If I got you right, you would like to make some kind of high thoughput communication between your STM and FPGA by mapping some memory in the FPGA to STM's hyperbus master interface? Well, I think that this is possible to do. Even more, this task doesn't look very complex. STM sends to your slave a ddr command, that is center-aligned to the clock, that means that you can easily capture the command by incoming clock. At the time of transmission slave just have to send data in ddr mode and toggle RWDS, this is also easy to do, as RWDS is edge-aligned to the outgoing data. Though I have no experience with STM's hyperbus controller, keep in mind that probably you will have to implement some kind of stub for configuration register access to make STM happy.

[toozie21]

@OVGN Thanks for the quick response. Correct, we were looking for a decent way to stream data from the STM to the FPGA. We were originally going to use QSPI, but the Xilinx core does not allow for slave mode. So then we figured we would look at HyperBUS since the STM will be using it to interface with some RAM, we might as well use it to interface with the FPGA as well (since we were going to have to do core development whether sticking with QSPI or going the HyperBus route).

For now I think that we were interested in just transmitting from the STM to the FPGA, so it should actually simplify things even more. I will have to look into the HyperBus protocol a little more, but what you are saying does make sense. I am a little surprised that there isn't a core out there to do this, but honestly, how many people are using HyperBus to begin with, let alone to receive data on the FPGA, not interact with a RAM/Flash.

Thanks for the insights, that was very helpful!

[OVGN]

Hi, @toozie21

So then we figured we would look at HyperBUS since the STM will be using it to interface with some RAM, we might as well use it to interface with the FPGA as well (since we were going to have to do core development whether sticking with QSPI or going the HyperBus route).

HyperBus allows to have multiple slaves on the same bus. I think this is possible to share the same bus between FPGA and HyperRAM, of course if STM provides additional CS lines. Also HyperBus will be faster than common QSPI.

I am a little surprised that there isn't a core out there to do this, but honestly, how many people are using HyperBus to begin with, let alone to receive data on the FPGA, not interact with a RAM/Flash.

Probably because HyperBus was designed to be more a memory interface. You will hardly find for example DDR4 memory slave interface anywhere else than on RAM.

Thanks for the insights, that was very helpful!

Sure, you are welcome.