Open AnttiLukats opened 1 year ago
Yes, I'm going to create several sets of sources to support different Vivado versions. HDL sources are going to be the same, but looks like I have to fix something in .tcl or .xml files.
Yes, I think it is something in the TCL portion of the core,if lucky you can create a core that is compatible with both versions.
Any good news on the new version update?
Hello,
I also face with the same problem. Would be really appreciated if you could fix this issue. I have also tried to solve the issue, though.
I have been using OpenHBMC on Vivado 2022.2 and 2023.1. The problem is in bd.tcl file as @AnttiLukats mentioned. A temporary workaround is to comment out the parts of the OpenHBMC/bd/bd.tcl file that does the address propagation. This solves the problem but address widths need to be handled manually. I have attached a patch for changes that I did. bd_tcl.patch
the current version does not work with Vivado 2022.2 steps to reproduce: take GIT files, create project in 2020.2, change constraints compile test with real hardware CR00107 all working open project in 2022.2, upgrade IP run the flow Error running propagate TCL procedure......................
Any chances this issue will be resolved in near future? would be nice to see support in recent release of Vivado!
UPDATE: the issue seems to be related to ADDRESS MAP. If OpenHBMC is "unassigned" in memory map view then all runs to bitgen without errors, well the design will not work, but it emits also no error. Assigning the memory regions will trigger error and the memory regions will be unassigned again automatically.