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OVGN / OpenHBMC

Open-source high performance AXI4-based HyperRAM memory controller
Apache License 2.0
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Getting HBMC working on a TE0725 (219) trenz board. #9

Open MenialJoe opened 2 years ago

MenialJoe commented 2 years ago

Hi,

Has anyone got OpenHBMC working for Trenz TE=0725 board?

I have been trying to get this to work for days, but no luck, the cypress chip onboard(8M) needs 0 and 180 deg clock phases... but the IP block takes 0 and 90.

Is it possible to use OpenHBMC with the Cypress chip?

Chip P/N: S27KS0641DPBHI000

After IP block has been added in Vivado 2020.2 following the instructions on the OpenHBMC project page it synths / implements and the 8M is by default added ad memoryaddress: 0x7600000 in the microblaze memorymap. Exporting the board specs after that and .bin / .mmi files to XSDK(VITIS) the debugger in XSDK(VITIS) gets immediate failure if i try to access memory location 0x76000000 and above.

Oh and clocks p & n to the IP block + the iserdes is: clk_0 = 88.888.. MHz clk_90 = 88.888 MHz, 90 deg rel to clk_0 clk_iserdes is = 266MHz, 0 deg rel to clk_0;

All generated from same MMCM clk_wiz block.

And microblaze and everything else like AXI running on a 100MHz clock from the same clk_wiz instance.

Any ideas?

Thanks!

OVGN commented 2 years ago

Hello!

Is it possible to use OpenHBMC with the Cypress chip?

Sure.

Any ideas?

I need a bit more information about your IP core configuration. Can you share your project? For example, Edit IP - Controller - Memory Clock Frequency - this parameter should be 88888888. Have you fixed this parameter?

AnttiLukats commented 1 year ago

Was the problem with the IP core and TE0725 resolved? I am the designer of TE0725 and would love to know.. We just verified OpenHBMC working on CR00107, we can reverify on TE0725 also, currently it's in the TODO list with a low prio.