FPGA Research

[lewismcnish]

Overview

Complete some introductory research on how an FPGA works and how this needs to be programmed (Use of AMD Vitis) can this be started on a machine locally before setup of the university workstation. It would be useful to document this and have a copy on Github and teams. This is an area we don't have a lot of knowledge on so researching and laying out a plan of action is the first step (if assistance is required ask Lewis, and inform on the plan of action)

Requirements

(In order of importance)

1. Complete research on how FPGA's work and how to program them
2. write a short document explaining this process and a plan of action

Definition of Done

(List the characteristics of the finished work)

1. Document with description of how to use the FPGA
2. Plan of action on how to carry out this process
3. Discuss with Lewis

Resources

This may be of Interest http://www.ee.ic.ac.uk/pcheung/teaching/ee2_digital/Lecture%202%20-%20Introduction%20to%20FPGAs.pdf

[JazzyMaxine]

@lewismcnish Would you be able to share the name of the FPGA we will have on board so that we can make sure the things we learn are relevant? The lecture you linked mentioned a few types, and some types might use different software to configure them.

[lewismcnish]

Will send this in the morning can't find the exact specs atm it's int he teams somewhere under detailed design if you want to go digging

[lewismcnish]

@JazzyMaxine should just be the AMD Xilinx Zynq 7030 SoC can't find an exact description of FPGA but hopefully you can find it from that info

[JazzyMaxine]

From some precursory research, I have the following points of understanding which we can use to structure our meeting this evening:

• We will be using AMD Vitis™ AI Software to configure our AMD FPGA with the neural net.
• Because our neural net is made in Tensorflow, we will use Model Zoo to convert it to a format that AMD Vitis™ AI can work on.
• We will then optimise, quantise, and compile our program into bytecode to configure the FPGA.
• We can run the FPGA using the AMD Vitis™ AI runtime, and it has a profiler we can use to try and improve efficiency (if we need to at that point, the model is kinda small and it'll already have been optimised quite a bit by the earlier steps).

Once we get it working in the runtime, I imagine we'll want to write the entry and exit points and test it on the hardware directly (without the Vitis runtime).