Little-endian bit order

[pavel-kirienko]

This changeset is a visual aid to the ongoing discussion at https://forum.uavcan.org/t/big-endian-vs-little-endian-in-the-context-of-bit-level-encoding/428. The question of the bit order suddenly became very critical because my work on the transport layer of Libcanard v1 has been completed and the next step is to implement the primitive serialization logic. To do that, I need to know first what the bit order going to be, to avoid changing the implementation later.

I dug into this question some more and also poked Kent Lennartsson of Kvaser for advice. It's Sunday so there's no response yet but let's hope he has time to look into it eventually.

One important thing to consider is that CANopen relies on the little-endian bit order, as I indicated in my today's post in the linked thread:

To reproduce the example from the CANopen spec:

# dsdl/Test.1.0.uavcan
uint10 value

The current, big-endian serialization logic yields this:

$ uvc dsdl-gen-pkg dsdl_src/dsdl/
$ python3
>>> import pyuavcan, dsdl
>>> [bytes(x) for x in pyuavcan.dsdl.serialize(dsdl.Test_1_0(0x21C))]
[b'\x1c\x80']  # CANopen would have yielded b'\x1c\x02'

The version implemented in this PR yields this:

$ python3
>>> import pyuavcan, dsdl
>>> [bytes(x) for x in pyuavcan.dsdl.serialize(dsdl.Test_1_0(0x21C))]
[b'\x1c\x02']  # Compatible with CANopen

A side effect of this change is that we can no longer conveniently represent serialized values as bit strings because our left-to-right positional numeral systems are inherently big-endian.

I invite @thirtytwobits and his colleague whose GitHub handle I do not have to evaluate this.

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[coveralls]

Pull Request Test Coverage Report for Build 747

• 56 of 56 (100.0%) changed or added relevant lines in 2 files are covered.
• 27 unchanged lines in 12 files lost coverage.
• Overall coverage decreased (-0.04%) to 86.145%

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Files with Coverage Reduction	New Missed Lines	%
pyuavcan/presentation/_port/_subscriber.py	1	82.46%
pyuavcan/transport/can/media/socketcan/_socketcan.py	1	82.11%
.test_dsdl_generated/uavcan/register/Access_1_0.py	1	95.74%
.test_dsdl_generated/uavcan/si/sample/angular_velocity/Scalar_1_0.py	1	83.33%
.test_dsdl_generated/uavcan/si/sample/duration/Scalar_1_0.py	1	83.33%
.test_dsdl_generated/uavcan/si/sample/voltage/Scalar_1_0.py	1	83.33%
.test_dsdl_generated/uavcan/si/unit/energy/Scalar_1_0.py	1	83.67%
.test_dsdl_generated/uavcan/si/unit/voltage/Scalar_1_0.py	1	83.67%
pyuavcan/transport/serial/_serial.py	2	93.98%
pyuavcan/_cli/_main.py	3	91.67%
<!--	Total:	27		-->

Totals
Change from base Build 745:	-0.04%
Covered Lines:	18373
Relevant Lines:	20578

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