OpenDGPS / zynq-axi-dma-sg

Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020
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Discontinuities in saved data with AXI DMA in cyclic Scatter/Gather Mode #4

Open rjmigliori opened 5 years ago

rjmigliori commented 5 years ago

HI OpenDGPS, I'm trying to save AXI4 stream data to memory using the AXI DMA engine on a Red Pitaya, which has I believe a Zynq 7010 SoC.

I've had some luck developing a project to do this based on your code, but there are strange and inexplicable discontinuities in the data saved to memory by the DMA engine, as in this figure.

In order to discern the nature of these discontinuities, I built a vivado program which does the following

Here is the corresponding block diagram, and address editor.

Based on your code, I wrote a c program HP0_DMA_SG.c that does the following

The python client determines where (i.e. at what index) the discontinuities are in the received data and the computes the spacing between them. The distance between discontinuities appears to be a function of, and sometimes equivalent to, the number of bytes transferred by each descriptor

Here is a plot of the received data, with discontinuities indicated as red dots/vertical lines, in a test where each descriptor was to transfer 1024 bytes (256 integers). Also notice in this figure where the signal drops to zero - I believe this is because the fourth descriptor is for some reason not writing to memory.

In the provided figure above, the red dots indicate the positions of discontinuities. Here are their positions and the spacing between them:

Discontinuity index, Discontinuity spacing 
249
250
505, 505-249=256
506
761, 761-505=256
762
767, 767-761=6
768

Notice that some of the discontinuities are 256 integers, or 1024 bytes, apart.

Additionally, I believe that the stream (or something) is not being flushed properly when I reset the DMA engine. I.e., I think the BD chain is retaining data after, even after I halt and reset it. I'll illustrate this with an example

I would really appreciate some help debugging this discontinuity issue. I understand that this is a lot of information to process. Please let me know if anything I've said deems further clarification or explanation, I'm happy to answer any questions you have.

Thanks!

abuzarshah963 commented 5 years ago

Hi rjmigliori, I am also working on same thing. I have achieved continuous samples from PL to PS (MM2S and S2MM) and successfully transferred over ethernet. You have to make an application with "LWIP echo server" and add the attached three files. Then using putty (baud rate 115200, COM3) you will get the data by uncommenting line *"//xil_printf("%d,",impval);" in echo.c** Else you can detect live data on matlab or labview by using TCP protocol with board IP "192.168.1.10", subnet mask "255.255.255.0" and GW "192.168.1.1"

Note: "I have sent sine wave of 5MHz from zedboard over ethernet server"

image

code_Eth.zip

abuzarshah963 commented 5 years ago

"LWIP echo server" in SDK (Vivado 2018.3 preferably).

huzaifasajids commented 4 years ago

Hi Abuzar, I'm working on exactly the same project as yours. Would love to get some help. If you can, please contact me through email(mentioned on my profile). Thanks.

abuzarshah963 commented 4 years ago

Hi Abuzar, I'm working on exactly the same project as yours. Would love to get some help. If you can, please contact me through email(mentioned on my profile). Thanks.

I have attached zip file with my comment. Refer to my reply.

huzaifasajids commented 4 years ago

yeah, I saw that. That's why I am contacting you now. Would have been excellent if you added the vivado design / simulink design to the zip as well. I'm trying to run your code but am probably making some mistake in the design.

rjmigliori commented 4 years ago

@abuzarshah963 I'll have to take a look at this at some point. Also the vivado design would certainly be useful to see as well. Thanks for replying!

abuzarshah963 commented 4 years ago

yeah, I saw that. That's why I am contacting you now. Would have been excellent if you added the vivado design / simulink design to the zip as well. I'm trying to run your code but am probably making some mistake in the design.

Block diagram is the same as attached with hyperlink by rjmigliori.

abuzarshah963 commented 4 years ago

yeah, I saw that. That's why I am contacting you now. Would have been excellent if you added the vivado design / simulink design to the zip as well. I'm trying to run your code but am probably making some mistake in the design.

Block diagram is the same as attached with hyperlink by rjmigliori.

If still facing any problem, contact me via email. I'll share the design details with you.