Can PDO data be read and then sent?

[lhf739181583]

I wanted to use the master to read the data before sending it, but I found that the LRW was only available when run ec_send_processdata(). I tried to separate the LRD,LWR in ecx_main_send_processdata , but the result was not satisfactory

[ArthurKetels]

LRD, LWR, LRW are available for use in an application. But be aware that the conditions to use it need to be set-up correctly. All of these methods use logical addressing. And need the proper set-up of FMMU's in each slave so as to set the correct physical to logical mapping. If the result is not satisfactory then clearly you have not set the correct conditions.

[lhf739181583]

Thank you very much for your answer. I am curious why it is necessary to read when sending instead of reading before sending. Because in general, we need to obtain the information of the slave station first, after certain processing, and then send the control command to the slave station. If it is read when it is sent, isn't the control instruction we send at this time refer to the slave station state of the previous cycle

[ArthurKetels]

Perhaps it is time you read about the basic principles of EtherCAT. Slaves do not send packets, they only can add data to a packet that has been transmitted by the master. So the master sends a LRD or LRW packet, when it arrives at the slave it checks if the logical address range matches the slave FMMU configuration. When it does, it inserts the data at the right spot in the packet. This packet then travels through other slaves (who can also insert their piece of data) and lastly it ends up back at the master. The master reads the packet and copies the data from the slaves in the IO buffer.

Of course the master can decide the timing of the packets so the data will arrive to the application at the right time.

Again, all of this is perfectly explained in the open documents of the ETG.

[lhf739181583]

I know that the read and write of data is controlled by the master station, but generally after receiving the SM interrupt, the slave station will carry out some processing, and then write the data to the IO buffer similar to LAN9252 chip until the master station obtains the data. For example, the synchronization cycle is 1S, the current motor is 0 degrees, and you want to command the motor to rotate 1 degree in each cycle. Since SOEM defaults to LRW. After the packet reaches the slave station, get to the current Angle of the motor is 0 degrees, and let the motor rotate 1 degree. In this 1S cycle the motor has reached 1 degree position. But the master station at this time to obtain the motor is still 0 degrees(Because the Angle is the last time the master read or write). In this cycle, the motor is expected to rotate to 2°, and the detection error is 2°but the actual error is 1°. In this way, the control quantity calculated by the controller will lead to unsatisfactory control effect

[lhf739181583]

Thank you very much for your answer. At present, I have successfully separated LRD and LWR, and achieved satisfactory results. After testing, the above-mentioned lag problem has been avoided. The previous problem was that the synchronization points of the synchronization cycle would be confused after separation.

[lhf739181583]

SOEM is a perfect project, and I look forward to separating LRD and LRW in the later stage