Closed PKUZHOU closed 2 years ago
Hi, Thank you for the interest on CXL memory device. I'm sorry that we don't publicly share the performance number of the CXL device for some reasons. However, given CXL specification, the goal of pin-to-pin latency is close to 1 hop latency between CPUs.
I got it. Thank you for your kindly reply!
Hello, I noticed that there is a latency/bandwidth test step in the wiki. I do not have the CXL memory device at hand, but I am curious about the performance number of the CXL-memory product. Is it possible that you can share the results with me? Thank you!