Closed cindy-q closed 9 months ago
The DAC DDR core expects a fix14_0 data in a 16-bit AXIS bus. This fix corrects the bit selection such that the top 14 MSB of the quotient AXIS bus is selected.
The DAC DDR core expects a fix14_0 data in a 16-bit AXIS bus. This fix corrects the bit selection such that the top 14 MSB of the quotient AXIS bus is selected.