Closed mgwoo closed 5 years ago
Hi @mgwoo , thanks for pointing out this issue! The parser fails because of the /
symbol and I have fixed this error. Please download the latest repo and try again and let me know if the issue still exists.
Thanks!
Thanks for the quick response. I've tried again but parser generated below errors now ...
Failed to match : /
Parser error: syntax error, unexpected end of file, expecting ';' or ','
begin at line 68 col 16
end at line 68 col 17
Aborted (core dumped)
Could you include three delimiters ( '/', '[', ']' )? (It seems that both of wire and netlist definition could have a starting escape character ('\'), and then may have delimiters ( '/', '[', ']' ) )
Thank you.
Hi @mgwoo , could you try changing the two wire names to below:
wire \fifo_in/enq_i ;
wire \fifo_in/tail_r ;
According to the Verilog lexical convention There should be a space between the name and ;
in an escaped identifier. Please let me know if you get the same error after doing this.
Thanks!
Sorry. I did a mistake in the Verilog file. It is working well now..! Thanks for supporting this Verilog parser.
When are you planning to make this repo public? I'd like to change ben-marshall's Verilog-parser into this if possible.
Hi @mgwoo , we have submitted this Parser-Verilog to be reviewed by the OpenSTA author and OpenROAD team. This repo will be made public after it passes the review.
Thank you again for pointing out the problem!
Thank you very much! I'll close this issue.
I've found out that below wire definition with delimiter generated below problem. Could you fix this issue?
For example, below two wire definition generated below logs.
These generated below error.
OpenSTA's verilog parser could handle this, but ben-marshall's parser is not able to handle this...