Closed cyyself closed 6 months ago
This PR added RISC-V Integer Conditional Operations Extension, which is in the RVA23U64 Profile Mandatory Base. And the performance of conditional move instructions in micro-architecture is an interesting point to explore.
Zicond instructions added: czero.eqz, czero.nez
Changes based on spec: https://github.com/riscvarchive/riscv-zicond/releases/download/v1.0.1/riscv-zicond_1.0.1.pdf
The same PR also on gem5 upstream: https://github.com/gem5/gem5/pull/1078
This PR added RISC-V Integer Conditional Operations Extension, which is in the RVA23U64 Profile Mandatory Base. And the performance of conditional move instructions in micro-architecture is an interesting point to explore.
Zicond instructions added: czero.eqz, czero.nez
Changes based on spec: https://github.com/riscvarchive/riscv-zicond/releases/download/v1.0.1/riscv-zicond_1.0.1.pdf
The same PR also on gem5 upstream: https://github.com/gem5/gem5/pull/1078