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OpenXiangShan
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HuanCun
Open-source high-performance non-blocking cache
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misc: remove tllog, now it is located in utility
#131
wakafa1
closed
1 year ago
0
top-down: support elaborated top down
#130
Tang-Haojin
closed
1 year ago
0
请教一下为什么总线协议从Tilelink转向了CHI？
#129
clp510
closed
1 year ago
1
请教关于core_reset的问题
#128
user-stu-l
closed
1 year ago
2
请教一下关于接入Non-inclusive HuanCun作为L2 Cache Probe的问题
#127
FuWenyi
closed
1 year ago
4
code opt: add write api in FileRegisters
#126
Maxpicca-Li
closed
1 year ago
0
util: add FileRegisters and update the use in TestTop.scala
#125
Maxpicca-Li
closed
1 year ago
0
请教一下有关noninclusive 和inclusive的问题
#124
user-stu-l
closed
1 year ago
3
slice: <> usage has changed, unidirection should use :=
#123
Lemover
closed
1 year ago
1
slice: <> usage has changed, unidirection should use :=
#122
Lemover
closed
1 year ago
1
Add Topdown switch
#121
wakafa1
closed
1 year ago
0
TestTop: support standalone topo to integrate slave agent
#120
wakafa1
closed
1 year ago
0
Ready to integrate into XiangShan
#119
wakafa1
closed
1 year ago
0
Separate Utility submodule from HuanCun
#118
wakafa1
closed
1 year ago
2
merge mshr-action
#117
gravelcai
closed
1 year ago
0
Merge the latest nanhu
#116
gravelcai
closed
1 year ago
0
Support Chiseldb
#115
gravelcai
closed
1 year ago
0
Nanhu chiseldb
#114
gravelcai
closed
1 year ago
2
new chiseldb version
#113
gravelcai
closed
1 year ago
1
Use PipeFastArbiter replacing LatchFastArbiter
#112
gravelcai
closed
1 year ago
0
Merge latest nanhu to nanhu-pipe-arbiter
#111
gravelcai
closed
1 year ago
0
can i create slavenodes to replace the ram.nodes in the testtop?
#110
user-stu-l
closed
1 year ago
3
Fix the replacer bug under condition of clk_div_by_2
#109
gravelcai
closed
2 years ago
2
Update change of processing flow of get/put to nano-v2
#108
Ivyfeather
closed
2 years ago
1
misc: reverse clk_en input of STD_CLKGT
#107
wakafa1
closed
2 years ago
0
Modify and optimize the processing flow of get/put
#106
wakafa1
closed
2 years ago
0
misc: update chiseltest version in build.sc
#105
Ivyfeather
closed
2 years ago
3
cmo: rewrite logic
#104
wakafa1
closed
2 years ago
0
top-down: add counters for top-down
#103
Tang-Haojin
closed
2 years ago
0
Southlake cmo parallel
#102
gravelcai
closed
1 year ago
1
Southlake cmo
#101
gravelcai
closed
2 years ago
0
support cmo for single concurrency.
#100
gravelcai
closed
2 years ago
1
Add 'cmoIdx' field in class MSHRRequest. Add registers names 'ctl_bus…
#99
gravelcai
closed
2 years ago
1
Nanhu llc
#98
gravelcai
closed
2 years ago
1
Nanhu llc
#97
gravelcai
closed
2 years ago
0
BOP: add negtive prefetch offset
#96
linjuanZ
closed
2 years ago
2
fix ChiselDB core dumped bug
#95
huanglingfeng
closed
2 years ago
0
New Prefetchers
#94
zeal4u
closed
2 years ago
0
make test error, tried with java 1.8.0_292 and java 11, ubuntu16.04
#93
iamdotasb
closed
1 year ago
6
Added chisel-db to dump chisel data structures by DPI-C
#92
ljwljwljwljw
closed
2 years ago
0
util.sram: rm a r/w hazard mux which is not needed
#91
Lemover
closed
2 years ago
0
Revert "sram: add rand+lastcycle garbage value gen logic"
#90
AugustusWillisWang
closed
2 years ago
0
Mbist implement
#89
Siudya
closed
2 years ago
0
Fix for chipsalliance/chisel3#2515
#88
sequencer
closed
2 years ago
2
tllog: add default parameter to make vcs happy
#87
AugustusWillisWang
closed
2 years ago
0
nanhu bug fix
#86
wakafa1
closed
2 years ago
1
nanhu: merge non-inclusive
#85
wakafa1
closed
2 years ago
0
Nanhu
#84
ljwljwljwljw
closed
2 years ago
0
logger: add .v extension to verilog files
#83
poemonsense
closed
2 years ago
0
sram: add rand+lastcycle garbage value gen logic
#82
AugustusWillisWang
closed
2 years ago
0
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