search

OpenXiangShan / NEMU

Other
234 stars 90 forks source link

[Bug Report] mtval register incorrectly updated after illegal instruction exception triggered by executing c.lwsp with rd=x0 #584

Open fly-1011 opened 5 days ago

fly-1011 commented 5 days ago

Describe the bug

When testing XiangShan using NEMU as a reference model, an illegal instruction exception occurs when executing instruction c.lwsp zero, 0(sp) (which is illegal because rd = x0, violating the constraints in the RISC-V compressed ISA). NEMU does not correctly set the mtvalCSR during the illegal instruction exception.

To Reproduce

Run the following command to execute the test image with NEMU as the reference model:

./build/emu -b 0 -e 0 -i id_1046.img --diff /xs-env/XiangShan/ready-to-run/riscv64-nemu-interpreter-so

image image

Expected behavior

When an illegal instruction exception occurs, NEMU should set mtval to the encoding of the illegal instruction like xiangshan.

Actual Behavior

NEMU sets mtval to the encoding of the previous instruction jr tp (0x0000000000020067).

Necessary information on versions

Xiangshan:commit ea2894c8c273b00083141d9258b412ed910b28f9 (HEAD, origin/master, origin/HEAD)

Ready-to-run:commit 2ade2e3879e019f6400cb33efbb62513166d139b (HEAD, origin/master, origin/HEAD)

NEMU commit: 300b282c158dbd2d4bd23edf4f682b27a0d711be

Additional information

This is the test program id_1046.zip

fly-1011 commented 1 day ago

To isolate the issue and eliminate the influence of other instructions, I wrote a minimal assembly program specifically to test the mtval behavior:

.text
   .global _start
 _start:
    xor t0, t0, t0
    .word 0x4002  # c.lwsp zero, 0(sp)

end:
    j end

In this test, the machine code for the xor t0, t0, t0 instruction is 0x0052c2b3. After running the test, the result shows: image image

This confirms that NEMU did not update the mtval register with the machine code of the illegal instruction c.lwsp zero, 0(sp)that triggered the exception.