Mismatch in mstatus Register Value

[fly-1011]

Describe the bug

When I tested Xiangshan, I found that executing the csrrw sp, sstatus, a7 instruction would cause the value of the mstatus register to be inconsistent.

This is the test program：mstatus_test.zip

Error log or Screenshots

Note: This issue may be related to https://github.com/OpenXiangShan/XiangShan/issues/3934, but the previous issue has been submitted for fix.

Necessary information on versions ready-to-run:c1dc496545b9d62bb10264cd4485cb6fe7c60798

• NEMU version: 0b75a4555a4cac16247a5fe3659f52ea900729e8
• xiangshan: fcefab3267fdc4c23472db8e6bca6d6054242e8a

[lewislzh]

@fly-1011 Thank you for your issue. This is indeed a problem: in the case of dte close, only the wmask of sstatus should be modified rather than the write val. Additionally, when reviewing your test, it was observed that Spike clears the sdt logic during mret without considering the illegal scenario of mpp=3 and mpv=1. Upon checking the upstream repository, it was found that this issue was fixed just three weeks ago. The fix has now been cherry-picked into the XiangShan Spike repository.