关于Minjie 论文的疑问

[pengwubj]

论文中的有这样的描述： According to the RISC-V instruction set manuals, any store (PTE Write, Store Retire) before an explicit sfence.vma instruction may or may not take effect (Store Complete) in the virtual address translation process (TLB Page Walk).
我理解论文是在说sfence后的ptw 可能看到不store buffer中的请求。

在2019/2021的特权里看到： SFENCE.VMA orders only the local hart’s implicit references to the memory-management data structures. Executing an SFENCE.VMA instruction guarantees that any previous stores already visible to the current RISC-V hart are ordered before certain implicit references by subsequent instructions in that hart to the memory- management data structures. 这里我理解要求sfence后续的ptw 可以看到本hart的store buffer的内容或者store buffer 中的请求排空。

所以对这里的表述有些疑问。请问论文中的说法在spec的依据具体体现在哪里，谢谢。

[poemonsense]

我理解论文是在说sfence后的ptw 可能看到不store buffer中的请求。

According to the RISC-V instruction set manuals, any store before an explicit sfence.vma instruction or may not take effect in the virtual address translation process.

论文表达的意思是，在 sfence.vma 之前的 store，不一定会在被 TLB 看到。

[poemonsense]

可能是我们的表述上有歧义，这句话的背景是，如 Figure 3 所示，在没有执行 sfence.vma 的情况下，store 的结果有可能被TLB看到，也有可能没有被TLB看到。

对应的软件行为在 Section III.B a) 中做了更进一步的解释：

Linux chooses not to execute a memory-barrier instruction after allocating a new physical page to avoid flushing instructions until a page fault exception.

[pengwubj]

理解了 非常感谢