Question concerning AXI bus

[Jett-tu]

您好！ 在生成XSTop.v文件以后，我想简单的仿真下，就只是给了时钟和复位。如下所示: XSTop XSTop_inst ( .io_clock ( sys_clk ), .io_reset ( !sys_rst_n ), //io_sram_config, //input io_osc_clock, //output [13:0] io_pll_output, ); 其他的总线信号就没有列举出来，省略。sys_clk为30Mhz，sys_rst_n模拟外部案件。按下为低电平。 其他默认。 通过仿真来看，memory和peripheral总线都没有读和写的操作。 请问是否还需要给那些激励信号? [TRANSLATION]Hello!

After generating the XSTop.v file, I want to simply simulate, just give the clock and reset. It looks like this:

XSTop XSTop_inst

(

.io_clock ( sys_clk ),

.io_reset ( ! sys_rst_n ),

//io_sram_config,

//input io_osc_clock,

//output [13:0] io_pll_output,

);

The other bus signals are not listed and are omitted. sys_clk is 30Mhz and sys_rst_n simulates external cases. Press down to low level.

Other defaults.

According to the simulation, there are no read or write operations on the memory and peripheral buses.

Do you still need to give those incentive signals?

[poemonsense]

可以试一下都给上。 [TRANSLATION]You can try them all.

[Jett-tu]

您好： 我把memory_0_axi4总线和一个带AXI4总线的RAM连接在一起。 把peripheral_0_axi4总线通过Vivado的axi_interconnect连接到一个SD和uart16550上面。SD卡存放运行的指令。 dma_0_axi4的总线没有做处理。 input io_clock, 接30M的时钟信号。 input io_reset, 接复位信号，高复位 input [4:0] io_sram_config, 接5‘h0 input io_osc_clock, 接1’h0 output [13:0] io_pll_output, 默认 input [149:0] io_extIntrs, 将uart16550的中断信号接到这里

input io_systemjtag_jtag_TCK, input io_systemjtag_jtag_TMS, input io_systemjtag_jtag_TDI, output io_systemjtag_jtag_TDO_data, output io_systemjtag_jtag_TDO_driven, input io_systemjtag_reset, input [10:0] io_systemjtag_mfr_id, input [15:0] io_systemjtag_part_number, input [3:0] io_systemjtag_versio 这些信号是Jtag调试的信号。我都没有给激励。因为我不需要进行debug调试。

接完这些信号以后，从仿真软件上进行查看，依旧没有看到memory或peripheral总线上有读/写行为。请问是否还有那些信号给出激励需要。 [TRANSLATION]Hello:

I connected the memory_0_axi4 bus with a RAM with an AXI4 bus.

Connect the peripheral_0_axi4 bus to an SD and uart16550 via axi_interconnect of Vivado. The SD card stores the running instructions.

The bus of dma_0_axi4 is not processed.

input io_clock, connect 30M clock signal.

input io_reset, connect reset signal, high reset

input [4:0] io_sram_config, connect 5’h0

input io_osc_clock, connect 1’h0

output [13:0] io_pll_output, default

input [149:0] io_extIntrs, where the interrupt signal of uart16550 is received

input io_systemjtag_jtag_TCK,

input io_systemjtag_jtag_TMS,

input io_systemjtag_jtag_TDI,

output io_systemjtag_jtag_TDO_data,

output io_systemjtag_jtag_TDO_driven,

input io_systemjtag_reset,

input [10:0] io_systemjtag_mfr_id,

input [15:0] io_systemjtag_part_number,

input [3:0] io_systemjtag_versio

These signals are signals for Jtag debugging. I didn't even give incentives. Because I don't need to debug.

After receiving these signals, the emulation software still does not see any read/write behavior on the memory or peripheral bus. May I ask if there are any other signals that give the need for stimulation?

[poemonsense]

看起来可能是复位的问题。我们现在还没有开始处理X值复位的问题，默认是随机复位。可以加一下随机初始化。

+define+RANDOMIZE_GARBAGE_ASSIGN +define+RANDOMIZE_INVALID_ASSIGN +define+RANDOMIZE_MEM_INIT +define+RANDOMIZE_DELAY=0 +define+RANDOMIZE_REG_INIT

[TRANSLATION]It looks like it might be a reset issue. We haven't dealt with reset of the X value yet; the default is random reset. You can add a random initialization.

[Jett-tu]

不好意思，不太明白您的意思，这个随机初始化具体加在哪里？是加在XSTop.v这个文件，用define来进行定义。 还是在运行make verilog命令带上这些define？ [TRANSLATION]Sorry, I don't quite understand what you mean. Where is this random initialization specifically added? It is added to the file XSTop.v and defined using define.

Or do you run the make verilog command with the define?

[poemonsense]

我理解您那边的仿真，没有采用我们提供的环境。

如果采用VCS的话，可以用VCS的+define选项加上那些宏定义。不过，像您说的，也可以在XSTop.v里面通过define来定义，也没有问题 [TRANSLATION]I understand that your simulation did not adopt the environment we provided.

If you are using VCS, you can add those macro definitions using the +define option of VCS. However, as you said, it is also possible to define it in XSTop.v with no problem

[Jett-tu]

是的，我借助VCS和Vivado来进行仿真测试。 根据您这边的建议，我将define加在XSTop.v文件中的module XSTop的前面。 但是从总线上观测，两条总线上都不存在读/写的行为。 [TRANSLATION]Yes, I used VCS and Vivado for simulation testing.

According to your suggestion, I added define before module XSTop in the xstop.v file.

However, as observed from the bus, there is no read/write behavior on either bus.

[poemonsense]

您可以继续深入一下核心内部看一下信号情况。从目前给出的信息，我们无法判断问题 [TRANSLATION]You can go deeper into the core and look at the signaling. From the information given so far, we cannot judge the problem

[Jett-tu]

我的设想是这样的，两组总线都接到带AXI4的接口的RAM上面，我在testbench给出时钟和复位信号。 这样是否可以观测到总线的读写行为？ 另外，您们指令是放在哪里的？是通过那条总线去读取第一条指令的？ [TRANSLATION]My vision is that both buses are connected to RAM with an AXI4 interface, and I give clock and reset signals in testbench.

Is it possible to observe the read and write behavior of the bus?

Also, where do you put your instructions? Which bus is used to read the first instruction?

[poemonsense]

第一条指令的物理地址是0x1000_0000，会通过总线来读 [TRANSLATION]The first instruction has the physical address 0x1000_0000 and is read over the bus

[Jett-tu]

是Peripheral还是memory这条总线进行读操作？ [TRANSLATION]Is the Peripheral or memory bus used for read operations?

[poemonsense]

peripheral

[Jett-tu]

在模块中去追这个peripheral_0_araddr[30:0]这个信号初始是由那个模块的赋值的。感觉有点绕。 能否指出其初始值是在那个模块？ 当然我也可以把我的顶层和仿真顶层发给您，看是否哪里激励给的不正确。麻烦了！ [TRANSLATION]In the module to trace this peripheral_0_araddr[30:0] this signal was originally assigned by that module. It feels a little messy.

Can you tell us which module the initial value is in?

Of course, I can also send my top level and simulation top level to you to see if the incentives are not correct. Excuse me!

[Jett-tu]

我发现在香山很多模块中用到以下代码。 `ifdef RANDOMIZE_MEM_INIT integer initvar; initial begin

`RANDOMIZE_DELAY begin end

    for (initvar = 0; initvar < 64; initvar = initvar+1)
         ram[initvar] = {128 {$random}};
     reg_RW0_addr = {1 {$random}};
     end

endif 对于这个 #RANDOMIZE_DELAY begin end的作用我不是很清楚。 如果我在XSTop.v顶层+define+RANDOMIZE_DELAY=0。反而出现诸多错误。 [TRANSLATION]I found the following code used in many modules in Xiangshan. I'm not sure what this # 'RANDOMIZE_DELAY begin end does.

If I +define+RANDOMIZE_DELAY=0 at the top of XSTop.v. Instead, there are many errors.

[poemonsense]

可以参考 https://www.runoob.com/w3cnote/verilog-time-delay.html

[Jett-tu]

您好，请问三条总线的地址空间划分是怎么划分的。 当前我只知道外设总线的起始地址是31‘h1000_0000,那么它的终止地址是到哪里， 另外，memory总线和DMA的总线的地址是如何划分的。 [TRANSLATION]Hello, may I ask how to divide the address space of the three buses?

At the moment, I only know that the start address of the peripheral bus is 31’h1000_0000, so where is its end address?

Also, how the addresses of the memory bus and the DMA bus are divided.

[poemonsense]

• 外设是0x0 - 0x80000000
• 内存是0x80000000往上，最大支持36bit物理地址（可配置，按照PAddrBits）
• DMA支持从0x80000000往上的地址空间，访问DDR和Cache内的数据

[Jett-tu]

如果我挂一个DDR3的控制器，用于控制外围的DDR3颗粒，应该和DMA的总线连在一起。 而不是和memory的总线连在一起？可以这么理解？那memory总线是访问什么外设的？ [TRANSLATION]If I attach a DDR3 controller, which controls the peripheral DDR3 particles, it should be connected to the DMA bus.

Instead of connecting to the memory bus? Can you understand it that way? What peripherals does the memory bus access?

[poemonsense]

memory总线访问的是DDR。关于DMA，可以搜索一下DMA相关的内容 [TRANSLATION]The memory bus accesses the DDR. For DMA, do a search for DMA-related content

[Jett-tu]

你们测试coremark程序？你们的环境是怎么样的，我这边分数才0.29 [TRANSLATION]You test the coremark program? What's your environment like, my score is 0.29

[poemonsense]

可以百度搜索一下coremark相关的内容 [TRANSLATION]You can search on Baidu for coremark related content

[Jett-tu]

我这边coremark程序放在RAM，外设总线在0x10000000开始读取，外接一个uart。地址是0x44a00000。 这样地址分配是否合适？ [TRANSLATION]On my side, the coremark program is placed in RAM, the peripheral bus starts reading at 0x10000000, and an external uart is attached. The address is 0x44a00000.

Is this an appropriate address assignment?

[poemonsense]

fpga上地址空间配置是您自己决定的，只需要和香山设置的PMA不产生冲突就可以正常访问 [TRANSLATION]The address space configuration on the fpga is decided by you, and it can be accessed normally without conflict with the PMA set by the Xiangshan

[Jett-tu]

请问，香山设置的PMA地址分配说明是在哪里的？在那个文件可以具体看到，这样可以避免地址发生重叠。 [TRANSLATION]Excuse me, where is the PMA address assignment instruction set by Xiangshan? This can be seen in that file to avoid overlapping addresses.

[poemonsense]

可以用一下文件搜索的功能 [TRANSLATION]You can use the file search function

[Jett-tu]

我查找了一下，在PMA.scala这个文件有地址映射。我发现，从0x4000_0000到0x7fff_ffff。您这边映射到了PCIE。 这块地址空间和我映射的串口地址0x44a0_0000到0x44a0_ffff存在重叠是否有问题。 另外，PMA.scala中那些地址香山已经映射好的，不能用于映射其他外设地址。 [TRANSLATION]I looked it up and found that there is an address mapping in PMA.scala. I found that it went from 0x4000_0000 to 0x7fff_ffff. Your side maps to PCIE.

Is there an overlap between this address space and my mapped serial port address 0x44a0_0000 to 0x44a0_ffff?

Additionally, addresses in PMA.scala are already mapped and cannot be used to map other peripheral addresses.

[poemonsense]

只要不是reserved的域，都可以用。香山本身并不在乎外面是不是PCIE，具体可以百度看一下PMA相关的原理 [TRANSLATION]It can be used as long as the domain is not reserved. Xiangshan itself does not care whether the outside is PCIE, specific Baidu can take a look at the principle of PMA

[Jett-tu]

您好： 在对南湖版本进行软件仿真的时候，发现peripheral总线在读取1000_0000这个地址的64bit数据以后，后续就不再进行取指令的操作。用的是c0b2b80的版本。 另外不知方便提供一个简单的Vivado工程。例如简单打印Hello这类就行。 [TRANSLATION]Hello:

In the software simulation of Nanhu version, it is found that the peripheral bus will not fetch instructions after reading 64bit data of the address 1000_0000. The c0b2b80 version is used.

It is also convenient to provide a simple Vivado project. For example, simply printing a class such as Hello will do.

[poemonsense]

不好意思，我们目前没有现成的vivado工程可以提供

[Jett-tu]

理解理解，那前一个问题，你那有遇到过吗？

[poemonsense]

我们这边仿真上没有遇到过，可以看一下取指的数据是否是正确的，指令有没有正常执行

[Jett-tu]

您好： 我这边想问下，你们当前主分支上的南湖版本支持B扩展吗？

[poemonsense]

支持B和K扩展

[HUA-FENG1995]

请问怎么可以知道哪段地址是预留的呀，有相关的文档吗？ [TRANSLATION]How can I know which section of address is reserved? Is there any relevant document?

[poemonsense]

可以结合https://xiangshan-doc.readthedocs.io/zh_CN/latest/integration/soc/ 和 https://github.com/OpenXiangShan/XiangShan/blob/nanhu/src/main/scala/xiangshan/backend/fu/PMA.scala 理解

[HUA-FENG1995]

可以结合https://xiangshan-doc.readthedocs.io/zh_CN/latest/integration/soc/ 和 https://github.com/OpenXiangShan/XiangShan/blob/nanhu/src/main/scala/xiangshan/backend/fu/PMA.scala 理解

好的，我看看哈，谢谢啦

[HUA-FENG1995]

可以结合https://xiangshan-doc.readthedocs.io/zh_CN/latest/integration/soc/ 和 https://github.com/OpenXiangShan/XiangShan/blob/nanhu/src/main/scala/xiangshan/backend/fu/PMA.scala 理解

请问这是关于emu的地址段吗，有关于emu各地址段的信息吗？如果访问到保留段的地址emu一般会有什么表现呀？

[poemonsense]

保留的地址段会报access fault异常

[poemonsense]

emu里面的外设在SimMMIO.scala和SoC.scala里面，前者是Uart flash sdcard这一些，后者有plic clint这些cpu内部的 [TRANSLATION]The peripherals in emu are in SimMMIO.scala and SoC.scala. The former is Uart flash sdcard, and the latter is plic clint

[HUA-FENG1995]

SimMMIO.scala

好的，谢谢

[HUA-FENG1995]

emu里面的外设在SimMMIO.scala和SoC.scala里面，前者是Uart flash sdcard这一些，后者有plic clint这些cpu内部的

保留的地址段会报access fault异常 请问emu的保留地址段在那里可以查看？ [0x0000_0000，0x1000_0000） [0x2000_0000，0x3001_0000）这两个地址是保留的还是不存在的？

[poemonsense]

0x3800_0000 - 0x3fff_ffff是CPU内部的外设，包括PLIC, CLINT, Debug等。这部分SOC用不了，对SOC来说是CPU保留段

emu仿真的时候，会在SimMMIO里面添加一些仿真用的外设，仅仿真生效。make verilog产生的流片用代码，是不会有这些设备的。除了0x3800_0000 - 0x3fff_ffff以外的地址段，都可以自由分配

[0x0000_0000，0x1000_0000） [0x2000_0000，0x3001_0000）因为在我们的SOC中，是空地址，所以PMA默认设置为保留了，软件无法访问。这个可以根据SOC的实际需求做调整 [TRANSLATION]0x3800_0000-0x3fff_ffff is the CPU internal peripheral, including PLIC, CLINT, Debug, etc. This part of the SOC is not used, for the SOC is the CPU reserved segment

When emu is emulation, some peripherals for emulation will be added to SimMMIO, which is only effective for emulation. The make verilog stream code does not have these devices. All address segments except 0x3800_00000-0x3FFF_FFFF can be allocated freely

[0x0000_0000, 0x1000_0000) [0x2000_0000, 0x3001_0000) Because in our SOC, it is empty address, so PMA is reserved by default and cannot be accessed by software. This can be adjusted according to the actual needs of SOC

[HUA-FENG1995]

0x3800_0000 - 0x3fff_ffff是CPU内部的外设，包括PLIC, CLINT, Debug等。这部分SOC用不了，对SOC来说是CPU保留段

emu仿真的时候，会在SimMMIO里面添加一些仿真用的外设，仅仿真生效。make verilog产生的流片用代码，是不会有这些设备的。除了0x3800_0000 - 0x3fff_ffff以外的地址段，都可以自由分配

[0x0000_0000，0x1000_0000） [0x2000_0000，0x3001_0000）因为在我们的SOC中，是空地址，所以PMA默认设置为保留了，软件无法访问。这个可以根据SOC的实际需求做调整

我看pma中[0x0000_0000，0x1000_0000） [0x2000_0000，0x3001_0000）都设置了读写访问权限，我尝试用emu访问了下，emu挂死了，请问这正常吗？

[poemonsense]

PMA.scala里面，是以[base_addr, top_addr)中的top来设置PMA的。所以对应的是，[0x0000_0000，0x1000_0000） [0x2000_0000，0x3001_0000）都没有读写访问权限 [TRANSLATION]In scala, PMA is set as the top of [base_addr, top_addr), so [0x0000_0000, 0x1000_0000) [0x2000_0000, 0x3001_0000) do not have read and write access

[HUA-FENG1995]

PMA.scala里面，是以[base_addr, top_addr)中的top来设置PMA的。所以对应的是，[0x0000_0000，0x1000_0000） [0x2000_0000，0x3001_0000）都没有读写访问权限

哦哦哦，明白了，谢谢大佬。请问pma_1_addr的范围是[0x0000_0000，0x1000_0000），pma_3_addr的范围是[0x2000_0000，0x3001_0000）；还是pma_0_addr的范围是[0x0000_0000，0x1000_0000），pma_2_addr的范围是[0x2000_0000，0x3001_0000）？还有如果遇到软件无法访问，emu是会挂死吗？

[poemonsense]

前一个问题请 @good-circle 帮忙解答

遇到无法访问的地址，CPU会报access fault异常

如果没有设置对应的异常处理函数，那上电默认的mtvec/stvec都是0，就会导致emu跳转到0地址。0地址也会报access fault异常，然后进入死循环。现在difftest设置了长时间未提交指令的报错，由于这种情况下CPU一直在异常死循环，导致长时间未正常执行、提交指令，所以difftest框架会报错 [TRANSLATION]Please ask @good-circle to answer the previous question

The CPU will raise an access fault if it encounters an address that cannot be accessed

If the corresponding exception handling function is not set, the default mtvec/stvec on power up is 0, which will cause emu to jump to address 0. 0 address will also report an access fault exception, and then enter an endless loop. Now difftest has set an error that no instructions have been submitted for a long time. Because the CPU has been abnormally looping in this case, resulting in a long time of normal execution and submission of instructions, the difftest framework will report an error

[good-circle]

nanhu 架构实现的 PMA 采用类 PMP 的方式，可以参考 RISC-V 特权级手册中关于 PMP 的 TOR 匹配模式说明。PMA 条目 i 匹配的地址空间为 $pmaaddr_{i-1} \leqslant address < pmaaddr_i$；特别地，当 $i = 0$ 时，会匹配 $address < pmaaddr_0$ 的所有地址。

对于你提到的情况，如果 $pmaaddr_0$ 为 0x1000_0000，则 $\text{PMA}_0$ 的范围是 [0x0000_0000，0x10000000），其余 PMA 项可以同理得到。 [TRANSLATION]The PMA implemented by the nanhu architecture adopts a PMP-like manner, which can be referred to the TOR matching pattern description of PMP in the RISC-V privilege level manual. The address space matching PMA entry i is $pmaaddr{i-1} \leqslant address < pmaaddr_i$; In particular, when $i = 0$, all addresses with $address < pmaaddr_0$are matched.

For the case you mentioned, if $pmaaddr_0$is 0x1000_0000, then the range of $\text{PMA}_0$is [0x0000_0000, 0x1000_0000), and the same can be said for the rest of the PMA entries.

[HUA-FENG1995]

nanhu 架构实现的 PMA 采用类 PMP 的方式，可以参考 RISC-V 特权级手册中关于 PMP 的 TOR 匹配模式说明。PMA 条目 i 匹配的地址空间为 pmaaddri−1⩽address<pmaaddri；特别地，当 i=0 时，会匹配 address<pmaaddr0 的所有地址。

对于你提到的情况，如果 pmaaddr0 为 0x1000_0000，则 PMA0 的范围是 [0x0000_0000，0x1000_0000），其余 PMA 项可以同理得到。

好的，懂了，感谢两位大佬

[HUA-FENG1995]

PMA.scala里配置了[0x0-0x7FFF_FFFF）可读可写 addPMA(0x0L, range = 0x80000000L, a = 3, w = true, r = true) 我对[0x5000_0000，0x6000_0000)和[0x7000_0000，0x8000_0000)进行读访问时，emu报错。没有配置PMP。请问正常吗？ [TRANSLATION]scala is configured to be [0x0-0x7FFF_FFFF) readable and writable

addPMA(0x0L, range = 0x80000000L, a = 3, w = true, r = true)

emu gives an error when I read access to [0x5000_0000, 0x6000_0000) and [0x7000_0000, 0x8000_0000). PMP is not configured.

[AugustusWillisWang]

PMA.scala里配置了[0x0-0x7FFF_FFFF）可读可写 addPMA(0x0L, range = 0x80000000L, a = 3, w = true, r = true) 我对[0x5000_0000，0x6000_0000)和[0x7000_0000，0x8000_0000)进行读访问时，emu报错。没有配置PMP。请问正常吗？

请问测试使用的代码版本是？可以给下 commit ID 吗？

[HUA-FENG1995]

commit 03590d72cc8626dfa2d2185d11cfa5a408a62c07