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OpenXiangShan / XiangShan

Open-source high-performance RISC-V processor
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LLPTW: fix error state transition when the new llptw req is onlyStage1 #3025

Closed pxk27 closed 4 weeks ago

pxk27 commented 1 month ago

onlyStage1 reqs may be sent into LLPTW. Their state transition is similar to noS2xlate reqs'. Their state need to be addr_check rather than hptw_req

XiangShanRobot commented 1 month ago
[Generated by IPC robot] commit: 3e851592f9f064fb79f8eb53ec9255779a7b6442 commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
3e85159 1.821 0.448 2.054 1.173 2.950 2.500 2.291 0.923 1.376 1.265 3.448 2.667 2.398 2.940
master branch: commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
cd467f7 1.821 2.054 1.173 2.950 2.500 0.923 1.376 1.265 3.448 2.398 2.940
75b44a5 1.821 2.054 1.173 2.950 2.500 0.923 1.376 1.265 3.448 2.398 2.940
321866f 1.821 2.054 1.173 2.950 2.500 0.924 1.376 1.265 3.448 2.398 2.940
082b30d 1.821 0.448 2.054 1.173 2.950 2.500 2.291 0.923 1.376 1.265 3.448 2.667 2.398 2.940
0e28018 1.823 2.054 1.172 2.950 2.500 0.923 1.376 1.265 3.449 2.398 2.943
df7130a 1.823 0.448 2.054 1.172 2.950 2.500 2.292 0.923 1.376 1.265 3.449 2.656 2.398 2.943
b51ac1c 1.823 0.448 2.054 1.172 2.950 2.500 2.292 0.923 1.376 1.265 3.449 2.656 2.398 2.943
79fadd7 1.868 0.448 2.096 1.166 2.945 2.603 2.333 0.952 1.377 1.298 3.424 2.659 2.468 2.945
f48d8a2 1.868 0.448 2.096 1.166 2.945 2.603 2.333 0.952 1.377 1.298 3.424 2.659 2.468 2.945
4ccb2e8 1.868 0.448 2.096 1.166 2.945 2.603 2.333 0.951 1.377 1.298 3.424 2.659 2.468 2.945