OpenXiangShan / XiangShan

Open-source high-performance RISC-V processor
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VLSU: fix bug of vector load/store split & support for segment instruction exception #3033

Closed weidingliu closed 3 weeks ago

weidingliu commented 4 weeks ago
good-circle commented 4 weeks ago

Perhaps we can set it to draft first and modify it back after CI passes

XiangShanRobot commented 3 weeks ago
[Generated by IPC robot] commit: a58e4221ca1ee548313f3c9d8fabad32d35bd859 commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
a58e422 1.815 0.448 2.060 1.182 2.953 2.504 2.291 0.930 1.403 1.319 3.426 2.660 2.397 2.940
master branch: commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
31fae68 1.815 0.448 2.060 1.182 2.953 2.504 2.291 0.930 1.403 1.319 3.426 2.660 2.397 2.940
071c63e 1.815 0.448 2.060 1.182 2.953 2.504 2.291 0.930 1.403 1.319 3.426 2.660 2.397 2.940
6b742a1 1.821 0.448 2.054 1.173 2.950 2.500 2.291 0.923 1.376 1.265 3.448 2.667 2.398 2.940
dc30dd9 1.821 0.448 2.054 1.173 2.950 2.500 2.291 0.923 1.376 1.265 3.448 2.667 2.398 2.940
cd467f7 1.821 0.448 2.054 1.173 2.950 2.500 2.291 0.923 1.376 1.265 3.448 2.667 2.398 2.940
75b44a5 1.821 0.448 2.054 1.173 2.950 2.500 2.291 0.923 1.376 1.265 3.448 2.667 2.398 2.940
321866f 1.821 0.448 2.054 1.173 2.950 2.500 2.291 0.924 1.376 1.265 3.448 2.667 2.398 2.940
082b30d 1.821 0.448 2.054 1.173 2.950 2.500 2.291 0.923 1.376 1.265 3.448 2.667 2.398 2.940
0e28018 1.823 0.448 2.054 1.172 2.950 2.500 2.292 0.923 1.376 1.265 3.449 2.656 2.398 2.943
df7130a 1.823 0.448 2.054 1.172 2.950 2.500 2.292 0.923 1.376 1.265 3.449 2.656 2.398 2.943