vtype: fix bug when vsetvl instruction's rd and rs1 are x0

[Ziyue-Zhang]

• fix uop split bug for vsetvl when rd and rs1 are 0, the first uop use wrong source register
• fix vtype writeback logic, add mux to choose vtype from intExu or vfExu

[XiangShanRobot]

[Generated by IPC robot] commit: 95f13124788587d58c049fcb06d57280360ccbb3	commit	astar	copy_and_run	coremark	gcc	gromacs	lbm	linux	mcf	microbench	milc	namd	povray	wrf	xalancbmk
95f1312	1.815	0.448	2.060	1.182	2.953	2.504	2.291	0.930	1.403	1.319	3.426	2.660	2.397	2.940

master branch:	commit	astar	copy_and_run	coremark	gcc	gromacs	lbm	linux	mcf	microbench	milc	namd	povray	wrf	xalancbmk
202ef6b	1.815	0.448	2.060	1.182	2.953	2.504	2.291	0.930	1.403	1.319	3.426	2.660	2.397	2.940
4c46d75	1.815		2.060	1.182	2.953	2.504	2.291	0.930	1.403	1.319	3.426		2.397	2.940
807e518	1.815	0.448	2.060	1.182	2.953	2.504	2.291	0.930	1.403	1.319	3.426	2.660	2.397	2.940
5820cff	1.815	0.448	2.060	1.182	2.953	2.504	2.291	0.930	1.403	1.319	3.426	2.660	2.397	2.940
8daac0b
c41a9f7
31fae68	1.815	0.448	2.060	1.182	2.953	2.504	2.291	0.930	1.403	1.319	3.426	2.660	2.397	2.940
071c63e	1.815	0.448	2.060	1.182	2.953	2.504	2.291	0.930	1.403	1.319	3.426	2.660	2.397	2.940
6b742a1	1.821	0.448	2.054	1.173	2.950	2.500	2.291	0.923	1.376	1.265	3.448	2.667	2.398	2.940
dc30dd9	1.821	0.448	2.054	1.173	2.950	2.500	2.291	0.923	1.376	1.265	3.448	2.667	2.398	2.940