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OpenXiangShan / XiangShan

Open-source high-performance RISC-V processor
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L1CacheErrorInfo: code refactor for correct and convenient clockgate #3044

Closed Maxpicca-Li closed 3 months ago

Maxpicca-Li commented 3 months ago

change the valid in the Bundle to the valid out of Bundle used ValidIO.

XiangShanRobot commented 3 months ago
[Generated by IPC robot] commit: 0da2b8b97f2ad615b44fa9a1248b0b60760c42a4 commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
0da2b8b 1.808 0.447 2.043 1.187 2.938 2.508 2.291 0.921 1.369 1.441 3.454 2.658 2.399 2.932
master branch: commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
a7828dc 0.921 2.932
9f598f8
e975de6 1.808 0.447 2.043 1.187 2.938 2.508 2.291 0.921 1.369 1.441 3.454 2.658 2.399 2.932
ff9b84b 0.447 2.043 1.187 2.291 0.921 1.369 3.454 2.658 2.932
3bec463 1.808 0.447 2.043 1.187 2.938 2.508 2.291 0.921 1.369 1.441 3.454 2.658 2.399 2.932
2d12882 0.447 2.043 1.187 2.291 0.921 1.369 3.454 2.658 2.932
ef14270 1.827 0.448 2.048 1.190 2.938 2.508 2.289 0.932 1.369 1.410 3.445 2.672 2.398 2.932
5c5f442 1.827 0.448 2.048 1.190 2.938 2.508 2.289 0.932 1.369 1.410 3.445 2.672 2.398 2.932
d67c873 1.827 0.448 2.048 1.190 2.938 2.508 2.289 0.932 1.369 1.410 3.445 2.672 2.398 2.932