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OpenXiangShan / XiangShan

Open-source high-performance RISC-V processor
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IssueQueue: when src0-2 read vector reg #0, transfer to src3 to read v0 #3060

Closed sinsanction closed 3 months ago

XiangShanRobot commented 3 months ago
[Generated by IPC robot] commit: 9d4f03d9c4420e24aef6cbd7456db59ade7596d4 commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
9d4f03d 1.808 0.447 2.043 1.187 2.938 2.508 2.197 0.921 1.369 1.441 3.454 2.658 2.399 2.932
master branch: commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
fcec058 0.921 2.932
0fbf39a 1.808 2.043 1.187 2.938 2.508 0.921 1.369 1.441 3.454 2.399 2.932
b37ee2e 1.808 2.043 1.187 2.938 2.508 2.197 0.921 1.369 1.441 3.454 2.658 2.399 2.932
b51d5c3 1.808 2.043 1.187 2.938 2.508 2.197 0.921 1.369 1.441 3.454 2.399 2.932
dd46182 1.808 0.447 2.043 1.187 2.938 2.508 2.197 0.921 1.369 1.441 3.454 2.658 2.399 2.932
49ceda6 1.808 0.447 2.043 1.187 2.938 2.508 2.197 0.921 1.369 1.441 3.454 2.658 2.399 2.932
a7828dc 1.808 0.447 2.043 1.187 2.938 2.508 2.291 0.921 1.369 1.441 3.454 2.658 2.399 2.932