search

OpenXiangShan / XiangShan

Open-source high-performance RISC-V processor
Other
4.45k stars 618 forks source link

VPU: fix vfreduction bug; remove redundant logic for scalar compute #3065

Closed lewislzh closed 2 weeks ago

lewislzh commented 2 weeks ago

fix vfreduction bug: Unordered reduction only generates fflags in the first round of uops, with the fflags outputs of other rounds set to 0; ordered reduction has only the lowest 5 bits of vfalu_0 valid in each uop, while all others are set to 0

XiangShanRobot commented 2 weeks ago
[Generated by IPC robot] commit: 5408c42c27af4305b5da754fdc330e90de7f3393 commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
5408c42 1.808 0.447 2.043 1.187 2.938 2.508 2.291 0.921 1.369 1.441 3.454 2.658 2.399 2.932
master branch: commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
b37ee2e
b51d5c3
dd46182
49ceda6 0.921
a7828dc 1.808 2.043 1.187 2.938 2.508 2.291 0.921 1.369 1.441 3.454 2.399 2.932
9f598f8
e975de6 1.808 0.447 2.043 1.187 2.938 2.508 2.291 0.921 1.369 1.441 3.454 2.658 2.399 2.932
ff9b84b 0.447 2.043 1.187 2.291 0.921 1.369 3.454 2.658 2.932
3bec463 1.808 0.447 2.043 1.187 2.938 2.508 2.291 0.921 1.369 1.441 3.454 2.658 2.399 2.932