StoreQueue: fix X when write StoreBuffer

[weidingliu]

If there is an inactive element in a vector access instruction, it will not be sent to the sta pipeline, so the data in the corresponding entry in the StoreQueue is invalid, and we use vecValid to differentiate between valid and invalid data in table entries.

For StoreQueue entries, vecValid depends on hasException, vecDataValid (whether the data in the table entry is valid or not), and isVec (whether it is a table entry for a vector instruction or not). vecDataValid is initialized to false, and will be set to true when sta writes back to the entry and the entry is a vector instruction.

Only vector instructions have invalid data in table entries, because we can't determine how many table entries are needed for a vector access uop at dispatch time.

[XiangShanRobot]

[Generated by IPC robot] commit: 41c3ba193a40be6b732f7ed1fde4771406587e04	commit	astar	copy_and_run	coremark	gcc	gromacs	lbm	linux	mcf	microbench	milc	namd	povray	wrf	xalancbmk
41c3ba1	1.808	0.447	2.043	1.187	2.938	2.508	2.197	0.921	1.369	1.441	3.454	2.658	2.399	2.932

master branch:	commit	astar	copy_and_run	coremark	gcc	gromacs	lbm	linux	mcf	microbench	milc	namd	povray	wrf	xalancbmk
fcec058	1.808		2.043	1.187	2.938	2.508		0.921	1.369	1.441	3.454		2.399	2.932
0fbf39a	1.808	0.447	2.043	1.187	2.938	2.508	2.197	0.921	1.369	1.441	3.454	2.658	2.399	2.932
b37ee2e	1.808	0.447	2.043	1.187	2.938	2.508	2.197	0.921	1.369	1.441	3.454	2.658	2.399	2.932
b51d5c3	1.808	0.447	2.043	1.187	2.938	2.508	2.197	0.921	1.369	1.441	3.454	2.658	2.399	2.932
dd46182	1.808	0.447	2.043	1.187	2.938	2.508	2.197	0.921	1.369	1.441	3.454	2.658	2.399	2.932
49ceda6	1.808	0.447	2.043	1.187	2.938	2.508	2.197	0.921	1.369	1.441	3.454	2.658	2.399	2.932
a7828dc	1.808	0.447	2.043	1.187	2.938	2.508	2.291	0.921	1.369	1.441	3.454	2.658	2.399	2.932