make verilog NUM_CORES=4 gets error

meiqin0 commented 5 months ago

Before start

[X] I have read the XiangShan Documents. 我已经阅读过香山文档。
[X] I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。
[X] I have searched the previous discussions and did not find anything relevant. 我已经搜索过之前的 discussions，并没有找到相关的。

Describe you problem

make verilog NUM_CORES=4 出错：

What did you do before

make verilog NUM_CORES=4 error： Error 1： [warn] There were 28 warning(s) during hardware elaboration. Exception in thread "main" java.lang.OutOfMemoryError: Java heap space at scala.collection.mutable.ArrayBuffer$.scala$collection$mutable$ArrayBuffer$$ensureSize(ArrayBuffer.scala:332) at scala.collection.mutable.ArrayBuffer.ensureAdditionalSize(ArrayBuffer.scala:77) at scala.collection.mutable.ArrayBuffer.addOne(ArrayBuffer.scala:146) at scala.collection.mutable.ArrayBuffer.addOne(ArrayBuffer.scala:43) at scala.collection.mutable.Buffer.append(Buffer.scala:43) at scala.collection.mutable.Buffer.append$(Buffer.scala:43) at scala.collection.mutable.AbstractBuffer.append(Buffer.scala:232) at firrtl.ir.Block.mapStmt(IR.scala:653) at firrtl.Mappers$StmtMagnet$$anon$3.map(Mappers.scala:31) at firrtl.Mappers$StmtMap$.map$extension(Mappers.scala:48) at firrtl.passes.CInferTypes$.infer_types_s$2(InferTypes.scala:149) at firrtl.passes.CInferTypes$.$anonfun$run$39(InferTypes.scala:159) at firrtl.passes.CInferTypes$$$Lambda$94647/0x0000000806b80040.apply(Unknown Source) at firrtl.ir.Module.mapStmt(IR.scala:1198) at firrtl.Mappers$ModuleMagnet$$anon$14.map(Mappers.scala:108) at firrtl.Mappers$ModuleMap$.map$extension(Mappers.scala:121) at firrtl.passes.CInferTypes$.infer_types$2(InferTypes.scala:159) at firrtl.passes.CInferTypes$.$anonfun$run$41(InferTypes.scala:162) at firrtl.passes.CInferTypes$$$Lambda$94644/0x0000000806c2b040.apply(Unknown Source) at scala.collection.immutable.List.map(List.scala:250) at scala.collection.immutable.List.map(List.scala:79) at firrtl.passes.CInferTypes$.run(InferTypes.scala:162) at firrtl.passes.Pass.execute(Pass.scala:14) at firrtl.passes.Pass.execute$(Pass.scala:14) at firrtl.passes.CInferTypes$.execute(InferTypes.scala:100) at firrtl.Transform.transform(Compiler.scala:280) at firrtl.Transform.transform$(Compiler.scala:280) at firrtl.passes.CInferTypes$.transform(InferTypes.scala:100) at firrtl.stage.transforms.ExpandPrepares.execute(ExpandPrepares.scala:19) at firrtl.Transform.transform(Compiler.scala:280) at firrtl.Transform.transform$(Compiler.scala:280) at firrtl.stage.transforms.ExpandPrepares.transform(ExpandPrepares.scala:7) 1 targets failed xiangshan[chisel3].test.runMain subprocess failed make: *** [build/rtl/SimTop.v] Error 1

之后修改了JVM的Xmx，大小为256G，不再报此错误，但出现了新错误： [TRANSLATION] After adjusting the JVM's Xmx to 256G, this error no longer occurs, but a new error has emerged: Error 2： FreeList: UncacheBuffer freelist, size 20 StoreQueue: size:64 Constantin initRead: LFSTEnable = 1 Constantin initRead: LFSTEnable = 1 Constantin initRead: LFSTEnable = 1 Constantin initRead: ForceWriteUpper_0 = 60 Constantin initRead: ForceWriteLower_0 = 55 Constantin initRead: StoreBufferThreshold_0 = 7 Constantin initRead: StoreBufferBase_0 = 4 Exception in thread "main" java.lang.NoClassDefFoundError: utility/ValidIODelay$ at xiangshan.backend.MemBlockImp.$anonfun$new$87(MemBlock.scala:503) at chisel3.experimental.prefix$.apply(prefix.scala:50) at xiangshan.backend.MemBlockImp.$anonfun$new$86(MemBlock.scala:503) at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) at xiangshan.backend.MemBlockImp.$anonfun$new$85(MemBlock.scala:503) at scala.Option.foreach(Option.scala:437) at xiangshan.backend.MemBlockImp.$anonfun$new$84(MemBlock.scala:502) at xiangshan.backend.MemBlockImp.$anonfun$new$84$adapted(MemBlock.scala:501) at scala.Option.foreach(Option.scala:437) at xiangshan.backend.MemBlockImp.(MemBlock.scala:501) at xiangshan.backend.MemBlock.$anonfun$module$4(MemBlock.scala:241) at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) at xiangshan.backend.MemBlock.module$lzycompute(MemBlock.scala:241) at xiangshan.backend.MemBlock.module(MemBlock.scala:241) at xiangshan.backend.MemBlock.module(MemBlock.scala:215) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$15(LazyModule.scala:335) at chisel3.Module$.do_apply(Module.scala:53) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$14(LazyModule.scala:335) at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$13(LazyModule.scala:335) at scala.Option.getOrElse(Option.scala:201) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$1(LazyModule.scala:333) at scala.collection.immutable.List.flatMap(List.scala:293) at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate(LazyModule.scala:309) at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate$(LazyModule.scala:306) at freechips.rocketchip.diplomacy.LazyModuleImp.instantiate(LazyModule.scala:396) at freechips.rocketchip.diplomacy.LazyModuleImp.$anonfun$x$22$1(LazyModule.scala:398) at chisel3.internal.plugin.package$.autoNameRecursivelyProduct(package.scala:48) at freechips.rocketchip.diplomacy.LazyModuleImp.(LazyModule.scala:398) at xiangshan.XSCoreImp.(XSCore.scala:74) at xiangshan.XSCore.$anonfun$module$1(XSCore.scala:71) at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) at xiangshan.XSCore.module$lzycompute(XSCore.scala:71) at xiangshan.XSCore.module(XSCore.scala:71) at xiangshan.XSCore.module(XSCore.scala:68) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$15(LazyModule.scala:335) at chisel3.Module$.do_apply(Module.scala:53) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$14(LazyModule.scala:335) at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$13(LazyModule.scala:335) at scala.Option.getOrElse(Option.scala:201) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$1(LazyModule.scala:333) at scala.collection.immutable.List.flatMap(List.scala:293) at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate(LazyModule.scala:309) at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate$(LazyModule.scala:306) at freechips.rocketchip.diplomacy.LazyModuleImp.instantiate(LazyModule.scala:396) at freechips.rocketchip.diplomacy.LazyModuleImp.$anonfun$x$22$1(LazyModule.scala:398) at chisel3.internal.plugin.package$.autoNameRecursivelyProduct(package.scala:48) at freechips.rocketchip.diplomacy.LazyModuleImp.(LazyModule.scala:398) at xiangshan.XSTile$XSTileImp.(XSTile.scala:93) at xiangshan.XSTile.$anonfun$module$1(XSTile.scala:167) at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) at xiangshan.XSTile.module$lzycompute(XSTile.scala:167) at xiangshan.XSTile.module(XSTile.scala:167) at xiangshan.XSTile.module(XSTile.scala:33) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$15(LazyModule.scala:335) at chisel3.Module$.do_apply(Module.scala:53) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$14(LazyModule.scala:335) at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$13(LazyModule.scala:335) at scala.Option.getOrElse(Option.scala:201) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$1(LazyModule.scala:333) at scala.collection.immutable.List.flatMap(List.scala:293) at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate(LazyModule.scala:309) at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate$(LazyModule.scala:306) at freechips.rocketchip.diplomacy.LazyRawModuleImp.instantiate(LazyModule.scala:405) at freechips.rocketchip.diplomacy.LazyRawModuleImp.$anonfun$x$23$2(LazyModule.scala:418) at chisel3.withClockAndReset$.apply(MultiClock.scala:26) at freechips.rocketchip.diplomacy.LazyRawModuleImp.$anonfun$x$23$1(LazyModule.scala:418) at chisel3.internal.plugin.package$.autoNameRecursivelyProduct(package.scala:48) at freechips.rocketchip.diplomacy.LazyRawModuleImp.(LazyModule.scala:417) at top.XSTop$XSTopImp.(Top.scala:164) at top.XSTop.$anonfun$module$1(Top.scala:301) at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) at top.XSTop.module$lzycompute(Top.scala:301) at top.XSTop.module(Top.scala:301) at top.SimTop.$anonfun$soc$2(SimTop.scala:32) at chisel3.Module$.do_apply(Module.scala:53) at top.SimTop.$anonfun$soc$1(SimTop.scala:32) at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) at top.SimTop.(SimTop.scala:32) at top.SimTop$.$anonfun$new$22(SimTop.scala:110) at freechips.rocketchip.diplomacy.package$.DisableMonitors(package.scala:228) at top.SimTop$.$anonfun$new$21(SimTop.scala:110) at chisel3.Module$.do_apply(Module.scala:53) at chisel3.stage.phases.Elaborate.$anonfun$transform$2(Elaborate.scala:40) at chisel3.internal.Builder$.$anonfun$build$1(Builder.scala:834) at scala.util.DynamicVariable.withValue(DynamicVariable.scala:59) at chisel3.internal.Builder$.build(Builder.scala:830) at chisel3.stage.phases.Elaborate.$anonfun$transform$1(Elaborate.scala:40) at scala.collection.immutable.List.flatMap(List.scala:293) at scala.collection.immutable.List.flatMap(List.scala:79) at chisel3.stage.phases.Elaborate.transform(Elaborate.scala:28) at chisel3.stage.phases.Elaborate.transform(Elaborate.scala:21) at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38) at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15) at firrtl.options.Translator.transform(Phase.scala:248) at firrtl.options.Translator.transform$(Phase.scala:248) at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15) at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280) at firrtl.Utils$.time(Utils.scala:181) at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280) at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:183) at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:179) at scala.collection.immutable.List.foldLeft(List.scala:79) at firrtl.options.DependencyManager.transform(DependencyManager.scala:269) at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255) at firrtl.options.PhaseManager.transform(DependencyManager.scala:443) at chisel3.stage.ChiselStage.run(ChiselStage.scala:46) at firrtl.options.Stage$$anon$1.transform(Stage.scala:43) at firrtl.options.Stage$$anon$1.transform(Stage.scala:43) at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38) at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15) at firrtl.options.Translator.transform(Phase.scala:248) at firrtl.options.Translator.transform$(Phase.scala:248) at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15) at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47) at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:183) at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:179) at scala.collection.immutable.List.foldLeft(List.scala:79) at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47) at logger.Logger$.$anonfun$makeScope$2(Logger.scala:137) at scala.util.DynamicVariable.withValue(DynamicVariable.scala:59) at logger.Logger$.makeScope(Logger.scala:135) at firrtl.options.Stage.transform(Stage.scala:47) at firrtl.options.Stage.execute(Stage.scala:58) at top.Generator$.execute(Generator.scala:34) at top.SimTop$.delayedEndpoint$top$SimTop$1(SimTop.scala:111) at top.SimTop$delayedInit$body.apply(SimTop.scala:97) at scala.Function0.apply$mcV$sp(Function0.scala:42) at scala.Function0.apply$mcV$sp$(Function0.scala:42) at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:17) at scala.App.$anonfun$main$1(App.scala:98) at scala.App.$anonfun$main$1$adapted(App.scala:98) at scala.collection.IterableOnceOps.foreach(IterableOnce.scala:575) at scala.collection.IterableOnceOps.foreach$(IterableOnce.scala:573) at scala.collection.AbstractIterable.foreach(Iterable.scala:933) at scala.App.main(App.scala:98) at scala.App.main$(App.scala:96) at top.SimTop$.main(SimTop.scala:97) at top.SimTop.main(SimTop.scala) Caused by: java.lang.ClassNotFoundException: utility.ValidIODelay$ at java.base/jdk.internal.loader.BuiltinClassLoader.loadClass(BuiltinClassLoader.java:581) at java.base/jdk.internal.loader.ClassLoaders$AppClassLoader.loadClass(ClassLoaders.java:178) at java.base/java.lang.ClassLoader.loadClass(ClassLoader.java:521) ... 141 more 1 targets failed xiangshan[chisel3].test.runMain subprocess failed make: *** [build/rtl/SimTop.v] Error 1

但是utility.ValidIODelay确实定义了 [TRANSLATION] However, utility.ValidIODelay is indeed defined

Environment

XiangShan branch: master
XiangShan commit id: commit 5794a5afda0002ad0014736a2b81824aab0616a0
NEMU commit id: dont care, but commit 01e78348a826a835d77af6dff7a69eaefa27fecb
SPIKE commit id: dont care
Operating System: Centos7.9
gcc version: 4.8.5
mill version: 0.11.7
java version: 11.0.22

Additional context

不知道是哪里的问题？

java 11/17都尝试过；物理内存512G

应该不是OS的问题，因为南湖版本编译单核、双核、四核都未出现此情况

[TRANSLATION]

I'm not sure what the issue is?

I have tried Java 11 and 17; the physical memory is 512G.

It should not be an OS issue, because the Nanhu version has compiled single-core, dual-core, and quad-core without encountering this situation.

Tang-Haojin commented 5 months ago

Have you tried make verilog NUM_CORES=1 in your environment?

cebarobot commented 5 months ago

考虑到您在使用的是 CentOS 7.9，感觉还是环境配置的有些问题。如果可能，我们还是推荐使用 Ubuntu 22.04。

Considering you are using CentOS 7.9, it is probably a environment problem. If possible, we recommand you to use Ubuntu 22.04.

能否请您提供下面这些命令的运行结果，来辅助我们判断环境问题： Could you please provide output of the below commands:

mill -i --version
java --version
echo $JAVA_HOME

meiqin0 commented 5 months ago

Have you tried make verilog NUM_CORES=1 in your environment?

尝试了，生成单核rtl是可以正常生成的，没有错误

[TRANSLATION]

I tried, and the single-core RTL can be generated normally without any errors.

meiqin0 commented 5 months ago

考虑到您在使用的是 CentOS 7.9，感觉还是环境配置的有些问题。如果可能，我们还是推荐使用 Ubuntu 22.04。

Considering you are using CentOS 7.9, it is probably a environment problem. If possible, we recommand you to use Ubuntu 22.04.

能否请您提供下面这些命令的运行结果，来辅助我们判断环境问题： Could you please provide output of the below commands:

mill -i --version
Mill Build Tool version 0.11.7
Java version: 11.0.22, vendor: Oracle Corporation, runtime: /home/jdk-11.0.22
Default locale: en_US, platform encoding: UTF-8
OS name: "Linux", version: 3.10.0-1160.el7.x86_64, arch: amd64
java --version
java 11.0.22 2024-01-16 LTS
Java(TM) SE Runtime Environment 18.9 (build 11.0.22+9-LTS-219)
Java HotSpot(TM) 64-Bit Server VM 18.9 (build 11.0.22+9-LTS-219, mixed mode)
echo $JAVA_HOME
/home/jdk-11.0.22

cebarobot commented 5 months ago

It's really strange... Have you tried to make clean or re-clone the XiangShan project?

这就很怪了。您尝试过 make clean 或者重新 clone 香山项目吗？

meiqin0 commented 5 months ago

It's really strange... Have you tried to make clean or re-clone the XiangShan project?

这就很怪了。您尝试过 make clean 或者重新 clone 香山项目吗？

尝试过make clean && rm -rf out ，也尝试过重新 clone代码。我刚才尝试，将jvm参数改成-Xmx200G -Xms200G 没有加-Xss参数，make verilog NUM_CORES=4也能正常编译，但是make emu或者simv会出现上述错误

[TRANSLATION]

I have tried make clean && rm -rf out, and also tried to re-clone the code. I just attempted to change the JVM parameters to -Xmx200G -Xms200G without adding the -Xss parameter. make verilog NUM_CORES=4 can compile normally, but make emu or simv results in the aforementioned error.

meiqin0 commented 5 months ago

It's really strange... Have you tried to make clean or re-clone the XiangShan project? 这就很怪了。您尝试过 make clean 或者重新 clone 香山项目吗？

尝试过make clean && rm -rf out ，也尝试过重新 clone代码。我刚才尝试，将jvm参数改成-Xmx200G -Xms200G 没有加-Xss参数，make verilog NUM_CORES=4也能正常编译，但是make emu或者simv会出现上述错误

[TRANSLATION]

I have tried make clean && rm -rf out, and also tried to re-clone the code. I just attempted to change the JVM parameters to -Xmx200G -Xms200G without adding the -Xss parameter. make verilog NUM_CORES=4 can compile normally, but make emu or simv results in the aforementioned error.

make emu/simv 会出现java ClassNotFoundException, 但是检查发现对应的object都存在，更改Xmx参数大小还会导致报错的objec不一样，不知道哪里出现的问题

[TRANSLATION]

Running make emu or simv results in a Java ClassNotFoundException, but upon checking, the corresponding objects are found to exist. Changing the size of the Xmx parameter can also cause different objects to be reported as errors, and I am unsure where the problem lies.

OpenXiangShan / XiangShan