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OpenXiangShan / XiangShan

Open-source high-performance RISC-V processor
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StoreQueue: sq entries with exception can deq without allvalid #3090

Closed good-circle closed 1 week ago

good-circle commented 1 week ago

However, databuffer.io.enq.bits.vecValid will be false so this store will not actually write into sbuffer.

XiangShanRobot commented 1 week ago
[Generated by IPC robot] commit: d96359afb816c370948284f4b4d2b66937869d8a commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
d96359a 1.809 0.452 2.052 1.196 2.951 2.499 2.197 0.930 1.382 1.407 3.436 2.653 2.398 2.941
master branch: commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
c08d352 1.809 0.452 2.052 1.196 2.951 2.499 2.197 0.930 1.377 1.407 3.436 2.653 2.398 2.941
87c5d21 1.805 0.452 2.052 1.196 2.951 2.499 2.199 0.930 1.377 1.407 3.436 2.653 2.398 2.941
864480f 1.809 0.452 2.052 1.196 2.951 2.499 2.199 0.930 1.377 1.407 3.436 2.653 2.398 2.941
69a3c27 1.805 0.452 2.052 1.196 2.951 2.499 2.197 0.930 1.377 1.407 3.436 2.653 2.398 2.941
a31db3f 1.805 0.452 2.052 1.196 2.951 2.499 2.197 0.930 1.377 1.407 3.436 2.653 2.398 2.941
5adc482 1.801 0.452 2.039 1.187 2.936 2.508 2.197 0.930 1.378 1.441 3.428 2.669 2.399 2.932
0d257fb 1.801 0.452 2.040 1.187 2.936 2.508 2.197 0.930 1.378 1.441 3.428 2.669 2.399 2.932
ba5ba1d 1.805 0.452 2.039 1.187 2.936 2.508 2.197 0.930 1.378 1.441 3.428 2.669 2.399 2.932
6613a2d 1.801 0.448 2.040 1.187 2.936 2.508 2.197 0.930 1.378 1.441 3.428 2.669 2.399 2.932
9810c04 1.805 0.448 2.040 1.187 2.936 2.508 2.197 0.930 1.378 1.441 3.428 2.669 2.399 2.932