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OpenXiangShan / XiangShan

Open-source high-performance RISC-V processor
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StoreUnit: fix bug when `lsq_replenish` of s2 fails to redirect #3113

Closed linjuanZ closed 5 days ago

linjuanZ commented 6 days ago

When access fault exception is reported on s2 of StoreUnit, the exception address will be written into exception buffer of StoreQueue. If the store is flushed on s2, the exception buffer must not be updated otherwise mtval csr might be of false value.

XiangShanRobot commented 5 days ago
[Generated by IPC robot] commit: 940e35781f4bba7e6b34481ea0eb1f795795f238 commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
940e357 1.812 0.451 2.047 1.199 2.941 2.507 2.196 0.934 1.373 1.397 3.181 2.669 2.403 2.961
master branch: commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
762f2b3 1.812 0.451 2.043 1.199 2.941 2.507 2.196 0.934 1.373 1.397 3.181 2.669 2.403 2.961
91f3148 1.812 0.451 2.047 1.199 2.941 2.507 2.196 0.934 1.373 1.397 3.181 2.669 2.403 2.961
d77cf63 1.812 0.451 2.043 1.199 2.941 2.507 2.196 0.934 1.373 1.397 3.181 2.669 2.403 2.961
d64fbe5 1.812 0.451 2.043 1.199 2.941 2.507 2.196 0.934 1.373 1.397 3.181 2.669 2.403 2.961
939a787 1.812 0.451 2.047 1.199 2.941 2.507 2.196 0.934 1.373 1.397 3.181 2.669 2.403 2.961
9705db6 1.812 0.451 2.047 1.199 2.941 2.507 2.196 0.934 1.373 1.397 3.181 2.669 2.403 2.961
78d7c65 1.812 0.451 2.043 1.199 2.941 2.507 2.196 0.934 1.373 1.397 3.181 2.669 2.403 2.961
5c1e8bf 1.812 0.451 2.043 1.199 2.941 2.507 2.196 0.934 1.373 1.397 3.181 2.669 2.403 2.961
7c26eb0 1.809 0.451 2.043 1.190 2.940 2.496 2.197 0.932 1.373 1.411 3.181 2.669 2.403 2.948
1436b76 1.811 0.451 2.047 1.190 2.940 2.496 2.197 0.932 1.373 1.411 3.181 2.669 2.403 2.948