Closed Tang-Haojin closed 1 day ago
maybe you can have a try on GitHub.com/chipsalliance/chisel-interface? This is designed for satisfying this problem
maybe you can have a try on GitHub.com/chipsalliance/chisel-interface? This is designed for satisfying this problem
Thanks! I hope I see it earlier.
XiangShan is using diplomacy and AXI4Bundle
in it, which is not completely equal with ChiselType in chisel-interface. Is rocket-chip or diplomacy planning to use chisel-interface? Maybe we can replace VerilogAXI4Record
with chisel-interface at that time.
Is rocket-chip or diplomacy planning to use chisel-interface? Maybe we can replace VerilogAXI4Record with chisel-interface at that time.
actually there is a diplomacy2 just in my brain. I don’t think rocket-chip would use that in a near future since there are a lot of backwards compatibility issue. My plan here is using the chisel-interface redesign the Edge
for a stable interface for chisel.
[Generated by IPC robot] commit: 0267a1baa676a81014f41e06562b8868d7e1df09 | commit | astar | copy_and_run | coremark | gcc | gromacs | lbm | linux | mcf | microbench | milc | namd | povray | wrf | xalancbmk |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0267a1b | 1.812 | 0.451 | 2.036 | 1.193 | 2.941 | 2.507 | 2.197 | 0.934 | 1.381 | 1.397 | 3.181 | 2.665 | 2.403 | 2.961 |
master branch: | commit | astar | copy_and_run | coremark | gcc | gromacs | lbm | linux | mcf | microbench | milc | namd | povray | wrf | xalancbmk |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
344cf5d | 0.451 | 2.036 | 1.184 | 2.938 | 2.497 | 2.196 | 0.935 | 1.381 | 1.280 | 3.183 | 2.666 | 2.961 | |||
c4a59f1 | 1.812 | 0.451 | 2.036 | 1.193 | 2.941 | 2.507 | 2.197 | 0.934 | 1.381 | 1.397 | 3.181 | 2.665 | 2.403 | 2.961 | |
5110577 | 1.812 | 0.451 | 2.043 | 1.199 | 2.941 | 2.507 | 2.196 | 0.934 | 1.373 | 1.397 | 3.181 | 2.669 | 2.403 | 2.961 | |
0d9b3da | 1.812 | 0.451 | 2.043 | 1.199 | 2.941 | 2.507 | 2.196 | 0.934 | 1.373 | 1.397 | 3.181 | 2.669 | 2.403 | 2.961 | |
842df08 | 1.812 | 0.451 | 2.043 | 1.199 | 2.941 | 2.507 | 2.196 | 0.934 | 1.373 | 1.397 | 3.181 | 2.669 | 2.403 | 2.961 | |
03b2841 | 1.812 | 0.451 | 2.047 | 1.199 | 2.941 | 2.507 | 2.196 | 0.934 | 1.373 | 1.397 | 3.181 | 2.669 | 2.403 | 2.961 | |
762f2b3 | 1.812 | 0.451 | 2.043 | 1.199 | 2.941 | 2.507 | 2.196 | 0.934 | 1.373 | 1.397 | 3.181 | 2.669 | 2.403 | 2.961 | |
91f3148 | 1.812 | 0.451 | 2.047 | 1.199 | 2.941 | 2.507 | 2.196 | 0.934 | 1.373 | 1.397 | 3.181 | 2.669 | 2.403 | 2.961 | |
d77cf63 | 1.812 | 0.451 | 2.043 | 1.199 | 2.941 | 2.507 | 2.196 | 0.934 | 1.373 | 1.397 | 3.181 | 2.669 | 2.403 | 2.961 | |
d64fbe5 | 1.812 | 0.451 | 2.043 | 1.199 | 2.941 | 2.507 | 2.196 | 0.934 | 1.373 | 1.397 | 3.181 | 2.669 | 2.403 | 2.961 |
[Generated by IPC robot] commit: 4901c12181adfb873d24e4d928182264b5466818 | commit | astar | copy_and_run | coremark | gcc | gromacs | lbm | linux | mcf | microbench | milc | namd | povray | wrf | xalancbmk |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
4901c12 | 1.805 | 0.458 | 1.995 | 1.189 | 2.928 | 2.494 | 2.224 | 0.927 | 1.356 | 1.389 | 3.173 | 2.664 | 2.401 | 2.963 |
master branch: | commit | astar | copy_and_run | coremark | gcc | gromacs | lbm | linux | mcf | microbench | milc | namd | povray | wrf | xalancbmk |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
195ef4a | 1.805 | 0.458 | 1.995 | 1.189 | 2.928 | 2.494 | 2.224 | 0.927 | 1.356 | 1.389 | 3.173 | 2.664 | 2.401 | 2.963 | |
6b46af8 | 1.804 | 0.458 | 1.995 | 1.189 | 2.928 | 2.494 | 2.224 | 0.927 | 1.378 | 1.389 | 3.173 | 2.664 | 2.401 | 2.963 | |
b92f844 | 1.804 | 0.458 | 1.995 | 1.189 | 2.928 | 2.494 | 2.224 | 0.927 | 1.368 | 1.389 | 3.173 | 2.664 | 2.401 | 2.963 | |
fe98272 | 1.827 | 0.451 | 2.036 | 1.184 | 2.938 | 2.497 | 2.196 | 0.935 | 1.381 | 1.280 | 3.183 | 2.666 | 2.403 | 2.961 | |
344cf5d | 1.828 | 0.451 | 2.036 | 1.184 | 2.938 | 2.497 | 2.196 | 0.935 | 1.381 | 1.280 | 3.183 | 2.666 | 2.403 | 2.961 | |
c4a59f1 | 1.812 | 0.451 | 2.036 | 1.193 | 2.941 | 2.507 | 2.197 | 0.934 | 1.381 | 1.397 | 3.181 | 2.665 | 2.403 | 2.961 | |
5110577 | 1.812 | 0.451 | 2.043 | 1.199 | 2.941 | 2.507 | 2.196 | 0.934 | 1.373 | 1.397 | 3.181 | 2.669 | 2.403 | 2.961 | |
0d9b3da | 1.812 | 0.451 | 2.043 | 1.199 | 2.941 | 2.507 | 2.196 | 0.934 | 1.373 | 1.397 | 3.181 | 2.669 | 2.403 | 2.961 | |
842df08 | 1.812 | 0.451 | 2.043 | 1.199 | 2.941 | 2.507 | 2.196 | 0.934 | 1.373 | 1.397 | 3.181 | 2.669 | 2.403 | 2.961 | |
03b2841 | 1.812 | 0.451 | 2.047 | 1.199 | 2.941 | 2.507 | 2.196 | 0.934 | 1.373 | 1.397 | 3.181 | 2.669 | 2.403 | 2.961 |
This PR generally contains three related parts.
To remove fragile
split_verilog.sh
, this PR switchs to seperated sv generation rather than an aggregated verilog. This also makes Xilinx Vivado happy.After split, we have to perform
sed
on amba signals for every sv files, which is really in elegant. Besides, thissed
method has also affected some unrelated signals as I recall, and that is unsafe.Hence, this PR also implements
VerilogAXI4Record
, which is automatically generated fromAXI4Bundle
and it works well withAXI4Bundle
thanks to DataView. The implicit dataviews are also generated automatically.Besides, this PR also uses xs_assert_v2 to replace xs_assert.